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A Very Compact Hardware Implementation of the KASUMI Block Cipher
Abstract : For mobile devices, this paper proposes a compact
hardware (H/W) implementation for the KASUMI block cipher, which is the
3GPP standard encryption algorithm. In [4], Yamamoto et al. proposed the
method of reducing temporary registers for the MISTY1 FO function
(YYI-08), and implemented a very compact MISTY1 H/W. This paper aims to
design the smallest KASUMI H/W by the application of YYI-08 to KASUMI,
which has a similarly structured MISTY1 FO function. We discussed the
applicability and found the problems on register competition and logical
equivalence in the simple application, so we propose the new YYI-08
improved for KASUMI and the compact H/W architecture. According to our
logic synthesis on a 0.11-μm ASIC process, the gate size is 2.99 Kgates,
which is the smallest as far as we know.
Cited literature [12 references]
https://hal.inria.fr/hal-01056077
Contributor : Hal Ifip <>
Submitted on : Thursday, August 14, 2014 - 5:59:44 PM
Last modification on : Friday, August 11, 2017 - 3:12:46 PM
Long-term archiving on: : Thursday, November 27, 2014 - 1:35:43 AM
Contributor : Hal Ifip <>
Submitted on : Thursday, August 14, 2014 - 5:59:44 PM
Last modification on : Friday, August 11, 2017 - 3:12:46 PM
Long-term archiving on: : Thursday, November 27, 2014 - 1:35:43 AM
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Distributed under a Creative Commons Attribution 4.0 International License