D. Antos, V. Rehak, and J. Korenek, Hardware Router's Lookup Machine and its Formal Verification, Conference Proceedings, 2004.

M. Ciobotaru, M. Ivanovici, R. Beuran, and S. Stancu, Versatile FPGA-based Hardware Platform for Gigabit Ethernet Applications, 6th Annual Postgraduate Symposium, 2005.

J. Ou and V. K. Prasanna, Rapid Energy Estimation of Computations on FPGA-based Soft Processors, 2004.

M. Werner, J. Richling, N. Milanovic, and V. Stantchev, Composability Concept for Dependable Embedded Systems, Proceedings of the International Workshop on Dependable Embedded Systems at the 22nd Symposium on Reliable Distributed Systems, 2003.

D. Teuchert and S. , Hauger: A Pipelined IP Address Lookup Module for 100 Gbps Line Rates and beyond, The Internet of Future, pp.148-157, 2009.

. Intel-white-paper, Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor, 2004.

N. Possley, Traffic Management in Xilinx FPGAs, 2006.

A. Kennedy, Low Power Architecture for High Speed Packet Classification, ANCS'08, 2008.

A. Iranli and M. Pedram, System-level power management: An overview, In: The VLSI Handbook Second Edition, 2006.