Structural DfT Strategy for High-Speed ADCs

Abstract : This paper presents a Design-for-Test (DfT) approach for folded ADCs. A sensor DfT circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of defects can be detected. A fault evaluation is done considering a behavioral model to compare the coverage of the proposed test approach with a functional test. Afterwards, a fault simulation is used on a transistor level implementation of the ADC to establish the optimum threshold limits for the DfT circuit that maximize the fault coverage figure.
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Communication dans un congrès
Luis M. Camarinha-Matos; Pedro Pereira; Luis Ribeiro. First IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Feb 2010, Costa de Caparica, Portugal. Springer, IFIP Advances in Information and Communication Technology, AICT-314, pp.529-536, 2010, Emerging Trends in Technological Innovation. 〈10.1007/978-3-642-11628-5_59〉
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Yolanda Lechuga, Roman Mozuelos, Mar Martínez, Salvador Bracho. Structural DfT Strategy for High-Speed ADCs. Luis M. Camarinha-Matos; Pedro Pereira; Luis Ribeiro. First IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Feb 2010, Costa de Caparica, Portugal. Springer, IFIP Advances in Information and Communication Technology, AICT-314, pp.529-536, 2010, Emerging Trends in Technological Innovation. 〈10.1007/978-3-642-11628-5_59〉. 〈hal-01060779〉

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