Spiking dynamic neural fields architectures on FPGA

Benoît Chappet de Vangel 1 Cesar Torres-Huitzil 2 Bernard Girau 1
1 CORTEX - Neuromimetic intelligence
Inria Nancy - Grand Est, LORIA - AIS - Department of Complex Systems, Artificial Intelligence & Robotics
Abstract : Neuromorphic engineering is a very active field aiming to design dedicated hardware architectures to simulate the tremendous power and complexity of the brain at real time speed. Many high scaled generic projects are a success but we focus on decentralized embeddable implementations of dynamic neural fields (DNF): a popular building blocks approach to simulate high level cognitive behaviours. The main difficulty of this approach is its mandatory all-to-all connectivity within the neural network which does not fit hardware constraints. Here we show that it is possible to decentralize the DNF computations using a cellular grid of spiking neurons with stochastic transmission mapped on a field programmable gate array (FPGA). The advantages of these randomly spiking dynamic neural fields (RSDNF) are a dedicated 1-bit probabilistic XY broadcast routing network with inherent synaptic weights computations that provides hardware compatibility thanks to the 4-neighbor cellular connectivity. Moreover, this implementation strategy exhibits fault tolerance properties but it is more area greedy and time consuming than an standard implementation that broadcasts neuron addresses and coordinates using the address event representation (AER) on a centralized bus.
Type de document :
Communication dans un congrès
Reconfig - International Conference on reconfigurable computing and FPGAs, Dec 2014, Cancun, Mexico. 2014
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Contributeur : Bernard Girau <>
Soumis le : lundi 6 octobre 2014 - 20:25:57
Dernière modification le : jeudi 11 janvier 2018 - 06:25:23


  • HAL Id : hal-01071873, version 1



Benoît Chappet de Vangel, Cesar Torres-Huitzil, Bernard Girau. Spiking dynamic neural fields architectures on FPGA. Reconfig - International Conference on reconfigurable computing and FPGAs, Dec 2014, Cancun, Mexico. 2014. 〈hal-01071873〉



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