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CHAMELEON: CHANNEL Efficient Optical Network-on-Chip

Abstract : The next generation of MPSoC points to the integration of thousands of IP cores, requiring high performance interconnect for high throughput communications. Optical on-chip interconnect enables significantly increased bandwidth and decreased latency in MPSoC. However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability. In this paper, we propose a novel optical interconnect named CHAMELEON. The interface simplifies the layout and allows the bandwidth between IP cores to be adapted according to the communication requirements. Compared to related networks, CHAMELEON demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.
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https://hal.inria.fr/hal-01075358
Contributor : Sébastien Le Beux <>
Submitted on : Friday, October 17, 2014 - 2:01:52 PM
Last modification on : Wednesday, July 8, 2020 - 12:44:00 PM
Long-term archiving on: : Sunday, January 18, 2015 - 10:26:13 AM

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Sébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, et al.. CHAMELEON: CHANNEL Efficient Optical Network-on-Chip. IEEE International Conference on Design Automation and Test in Europe (DATE), Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.317⟩. ⟨hal-01075358⟩

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