CHAMELEON: CHANNEL Efficient Optical Network-on-Chip

Sébastien Le Beux 1, 2, * Hui Li 1, 2 Ian O'Connor 1, 2 Kazem Cheshmi 3 Xuchen Liu 1, 2 Jelena Trajkovic 3 Gabriela Nicolescu 4
* Auteur correspondant
1 ECL - École Centrale de Lyon
2 INL - Institut des Nanotechnologies de Lyon
3 Concordia University [Montreal, Canada]
4 EPM - École Polytechnique de Montréal
Abstract : The next generation of MPSoC points to the integration of thousands of IP cores, requiring high performance interconnect for high throughput communications. Optical on-chip interconnect enables significantly increased bandwidth and decreased latency in MPSoC. However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability. In this paper, we propose a novel optical interconnect named CHAMELEON. The interface simplifies the layout and allows the bandwidth between IP cores to be adapted according to the communication requirements. Compared to related networks, CHAMELEON demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.
Keywords : MPSoC WDM Optical Network on Chip
Type de document :
Communication dans un congrès
IEEE International Conference on Design Automation and Test in Europe (DATE), Mar 2014, Dresden, Germany. 2014, 〈10.7873/DATE.2014.317〉
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Sébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, et al.. CHAMELEON: CHANNEL Efficient Optical Network-on-Chip. IEEE International Conference on Design Automation and Test in Europe (DATE), Mar 2014, Dresden, Germany. 2014, 〈10.7873/DATE.2014.317〉. 〈hal-01075358〉

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