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Design Space Exploration in an FPGA-Based Software Defined Radio

Abstract : The FPGA (Field Programmable Gate Array) technology is expected to play a key role in the development of Software Defined Radio (SDR) platforms. To this aim, leveraging the nascent High-Level Synthesis (HLS) tools, a design flow from high-level specifications to Register-Transfer Level (RTL) description can be thought. Based on such a flow, this paper describes the Design Space Exploration (DSE) that can be achieved using loop optimizations. The mainstream objective is to demonstrate the compile-time flexibility of an architecture when associated with a reconfigurable platform. Throughout both IEEE 802.15.4 and IEEE 802.11g waveform examples, we show how the FPGA resources can be tuned according to a targeted throughput.
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Submitted on : Thursday, November 20, 2014 - 4:53:35 PM
Last modification on : Thursday, January 20, 2022 - 4:20:29 PM
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Matthieu Gautier, Ganda Stephane Ouedraogo, Olivier Sentieys. Design Space Exploration in an FPGA-Based Software Defined Radio. Euromicro Conference on Digital System Design, Aug 2014, Verona, Italy. ⟨10.1109/DSD.2014.44⟩. ⟨hal-01084781⟩



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