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Translation Validation for Synchronous Data-flow Specification in the SIGNAL Compiler

van Chan Ngo 1 Jean-Pierre Talpin 1 Thierry Gautier 2
1 ESPRESSO - Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
2 TEA - Tim, Events and Architectures
Inria Rennes – Bretagne Atlantique , IRISA-D4 - LANGAGE ET GÉNIE LOGICIEL
Abstract : We present a method to construct a validator based on trans-lation validation approach to prove the value-equivalence of variables in the Signal compiler. The computation of output signals in a Signal program and their counterparts in the generated C code is represented by a Synchronous Data-flow Value-Graph (Sdvg). The validator proves that every output signal and its counterpart variable have the same val-ues by transforming the Sdvg graph.
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https://hal.inria.fr/hal-01087801
Contributor : van Chan Ngo <>
Submitted on : Wednesday, November 26, 2014 - 4:29:30 PM
Last modification on : Tuesday, June 15, 2021 - 4:26:57 PM
Long-term archiving on: : Friday, February 27, 2015 - 12:40:45 PM

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  • HAL Id : hal-01087801, version 1

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van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier. Translation Validation for Synchronous Data-flow Specification in the SIGNAL Compiler. 2014. ⟨hal-01087801⟩

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