Dedicating more silicon area to single thread perfor-mance will necessarily be considered as worthwhile in fu-ture – potentially heterogeneous – multicores. In particular, Value prediction (VP) was proposed in the mid 90's to en-hance the performance of high-end uniprocessors by break-ing true data dependencies. In this paper, we reconsider the concept of Value Predic-tion in the contemporary context and show its potential as a direction to improve current single thread performance. First, building on top of research carried out during the pre-vious decade on confidence estimation, we show that every value predictor is amenable to very high prediction accu-racy using very simple hardware. This clears the path to an implementation of VP without a complex selective reis-sue mechanism to absorb mispredictions. Prediction is per-formed in the in-order pipeline frond-end and validation is performed in the in-order pipeline back-end, while the out-of-order engine is only marginally modified. Second, when predicting back-to-back occurrences of the same instruction, previous context-based value predictors relying on local value history exhibit a complex critical loop that should ideally be implemented in a single cycle. To bypass this requirement, we introduce a new value predic-tor VTAGE harnessing the global branch history. VTAGE can seamlessly predict back-to-back occurrences, allowing predictions to span over several cycles. It achieves higher performance than previously proposed context-based pre-dictors. Specifically, using SPEC'00 and SPEC'06 benchmarks, our simulations show that combining VTAGE and a stride-based predictor yields up to 65% speedup on a fairly aggressive pipeline without support for selective reissue