Time-critical computing on a single-chip massively parallel processor

Benoît Dupont de Dinechin 1 Duco Van Amstel 2, 1 Marc Poulhies 1 Guillaume Lager 1
2 CORSE - Compiler Optimization and Run-time Systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : The requirement of high performance computing at low power can be met by the parallel execution of an application on a possibly large number of programmable cores. However, the lack of accurate timing properties may prevent parallel execution from being applicable to time-critical applications. We illustrate how this problem has been addressed by suitably designing the architecture, implementation, and programming model, of the Kalray MPPA®-256 single-chip many-core processor.The MPPA®-256 (Multi-Purpose Processing Array) processor integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These VLIW cores are distributed across 16 compute clusters and 4 I/O subsystems, each with a locally shared memory. On-chip communication and synchronization are supported by an explicitly addressed dual network-on-chip (NoC), with one node per compute cluster and 4 nodes per I/O subsystem. Off-chip interfaces include DDR, PCI and Ethernet, and a direct access to the NoC for low-latency processing of data streams.The key architectural features that support time-critical applications are timing compositional cores, independent memory banks inside the compute clusters, and the data NoC whose guaranteed services are determined by network calculus. The programming model provides communicators that effectively support distributed computing primitives such as remote writes, barrier synchronizations, active messages, and communication by sampling. POSIX time functions expose synchronous clocks inside compute clusters and mesosynchronous clocks across the MPPA®-256 processor.
Type de document :
Communication dans un congrès
European Design and Automation Association. Conference on Design, Automation & Test in Europe, Mar 2014, Dresden, Germany. pp.97:1-97:6, 2014, Proceedings of the Conference on Design, Automation & Test in Europe 2014. 〈http://www.date-conference.com/front〉
Liste complète des métadonnées

https://hal.inria.fr/hal-01090449
Contributeur : Duco Amstel <>
Soumis le : mercredi 3 décembre 2014 - 15:17:59
Dernière modification le : mercredi 11 avril 2018 - 01:52:44

Identifiants

  • HAL Id : hal-01090449, version 1

Collections

Citation

Benoît Dupont de Dinechin, Duco Van Amstel, Marc Poulhies, Guillaume Lager. Time-critical computing on a single-chip massively parallel processor. European Design and Automation Association. Conference on Design, Automation & Test in Europe, Mar 2014, Dresden, Germany. pp.97:1-97:6, 2014, Proceedings of the Conference on Design, Automation & Test in Europe 2014. 〈http://www.date-conference.com/front〉. 〈hal-01090449〉

Partager

Métriques

Consultations de la notice

171