A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design

Abstract : A system-on-chip (SoC) contains numerous intellectual property blocks, or IPs. Protocol mismatches between IPs may affect the system-level functionality of the SoC. Mismatches are addressed by introducing converters to control inter-IP interactions. Current approaches towards converter generation find limited practical application as they use restrictive models, lack formal rigour, handle a small subset of commonly encountered mismatches, and/or are not scalable. We propose a formal technique for SoC design using incremental converter synthesis. The proposed formulation provides precise models for protocols and requirements, and provides a scalable algorithm that allows adding multiple components and requirements to an SoC incrementally. We prove that the technique is sound and complete. Experimental results obtained using real-life AMBA benchmarks show the scalability and wide range of mismatches handled by our approach.
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ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, 2014, 20, pp.30. 〈10.1145/2663344〉
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https://hal.inria.fr/hal-01092255
Contributeur : Gregor Gössler <>
Soumis le : lundi 8 décembre 2014 - 14:38:41
Dernière modification le : mardi 9 décembre 2014 - 01:02:36

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Roopak Sinha, Alain Girault, Gregor Gössler, Partha Roop. A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design. ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, 2014, 20, pp.30. 〈10.1145/2663344〉. 〈hal-01092255〉

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