Adding a single state memory optimally accelerates symmetric linear maps

Alain Sarlette 1
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ENS Paris - École normale supérieure - Paris, UPMC - Université Pierre et Marie Curie - Paris 6, MINES ParisTech - École nationale supérieure des mines de Paris, Inria de Paris
Abstract : Previous papers have proposed to add memory registers to the dynamics of discrete-time linear systems in order to accelerate their convergence. In particular, it has been proved that adding one memory slot per agent allows faster convergence towards average consensus. We here prove that this situation cannot be improved by adding more memory slots, when the knowledge about the self-adjoint linear map to be accelerated reduces to bounds on its extreme eigenvalues.
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https://hal.inria.fr/hal-01093907
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Submitted on : Monday, December 28, 2015 - 5:56:26 PM
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  • HAL Id : hal-01093907, version 2
  • ARXIV : 1412.0402

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Alain Sarlette. Adding a single state memory optimally accelerates symmetric linear maps. IEEE Transactions on Automatic Control, Institute of Electrical and Electronics Engineers, 2016, 61 (11), pp.3533. ⟨hal-01093907v2⟩

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