V. H. Allan, R. B. Jones, R. M. Lee, and S. J. Allan, Software pipelining, ACM Computing Surveys, vol.27, issue.3, 1995.

F. André, M. Mallet, and . Peraldi-frati, A multiform time approach to real-time system modeling; Application to an automotive system, 2007 International Symposium on Industrial Embedded Systems, 2007.
DOI : 10.1109/SIES.2007.4297340

A. Beno??tbeno??t, V. Rehn-sonigo, and Y. Robert, Multi-criteria scheduling of pipeline workflows, Proceedings of the International Conference on Cluster Computing, 2007.

P. Calland, A. Darte, and Y. Robert, Circuit retiming applied to decomposed software pipelining. Parallel and Distributed Systems, IEEE Transactions on, vol.9, issue.1, pp.24-35, 1998.
URL : https://hal.archives-ouvertes.fr/hal-00856850

D. Carle, Y. Potop-butucaru, D. Sorel, and . Lesens, From dataflow specification to multiprocessor partitioned time-triggered real-time implementation, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00742908

P. Caspi, A. Curic, A. Magnan, C. Sofronis, S. Tripakis et al., From Simulink to SCADE/Lustre to TTA: a layered approach for distributed embedded applications, Proceedings LCTES, 2003.

K. Chatha and R. Vemuri, Hardware-software partitioning and pipelined scheduling of transformative applications. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.10, issue.3, pp.193-208, 2002.

Y. Chiu, C. Shih, and S. Hung, Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints, DATE, 2011.

P. Eles, A. Doboli, P. Pop, and Z. Peng, Scheduling with bus access optimization for distributed embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.8, issue.5, 2000.
DOI : 10.1109/92.894152

G. Fohler, A. Neundorf, K. Arzén, C. Lucarz, M. Mattavelli et al., EU FP7 ACTORS project. Deliverable D7a: State of the art assessment. Ch. 5: Resource reservation in real-time systems, 2008.

M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NP- Completeness, 1979.

F. Gasperoni and U. Schwiegelshohn, GENERATING CLOSE TO OPTIMUM LOOP SCHEDULES ON PARALLEL PROCESSORS, Parallel Processing Letters, pp.391-404, 1994.
DOI : 10.1142/S0129626494000363

E. Govindarajan, G. Altman, and . Gao, Minimizing register requirements under resourceconstrained rate-optimal software pipelining, Proceedings of the 27th annual international symposium on Microarchitecture, 1994.
DOI : 10.1145/192724.192733
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.41.2377

T. Grandpierre and Y. Sorel, From algorithm and architecture specification to automatic generation of distributed real-time executives, Proceedings MEMOCODE, 2003.

J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 2007.

R. Huff, Lifetime-sensitive modulo scheduling, Proc. of the ACM SIGPLAN '93 Conf. on Programming Language Design and Implementation, pp.258-267, 1993.
DOI : 10.1145/173262.155115
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.54.6852

W. Kim, D. Yoo, H. Park, and M. Ahn, SCC based modulo scheduling for coarse-grained reconfigurable processors, 2012 International Conference on Field-Programmable Technology, 2012.
DOI : 10.1109/FPT.2012.6412156

M. Lam, Software pipelining, Proceedings of the SIGPLAN 88 Conference on Programming Language Design and Implementation, pp.318-328, 1988.
DOI : 10.1145/989393.989420

C. Leiserson and J. Saxe, Retiming synchronous circuitry, Algorithmica, vol.9, issue.No. 1, pp.5-35, 1991.
DOI : 10.1007/BF01759032
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.368.3222

A. Monot, N. Navet, F. Simonot, and B. Bavoux, Multicore scheduling in automotive ECUs, Proceedings ERTSS, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00543179

. Muchnick, Advanced Compiler Design and Implementation, 1997.

D. Potop-butucaru, R. D. Simone, Y. Sorel, and J. Talpin, Clock-driven distributed realtime implementation of endochronous synchronous programs, ACM, editor, EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software, pp.147-156, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00485007

D. Potop-butucaru, A. Azim, and S. Fischmeister, Semantics-preserving implementation of synchronous specifications over dynamic TDMA distributed architectures, Proceedings of the tenth ACM international conference on Embedded software, EMSOFT '10, 2010.
DOI : 10.1145/1879021.1879048
URL : https://hal.archives-ouvertes.fr/inria-00544665

C. Pradalier, J. Hermosillo, C. Koike, C. Braillon, P. Bessì et al., The CyCab: a car-like robot navigating autonomously and safely among pedestrians, Robotics and Autonomous Systems, vol.50, issue.1, 2005.
DOI : 10.1016/j.robot.2004.10.002
URL : https://hal.archives-ouvertes.fr/inria-00182049

. Rau, Iterative Modulo Scheduling, International Journal of Parallel Programming, vol.3, issue.3, pp.3-64, 1996.
DOI : 10.1007/BF03356742
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.304.8660

B. Rau and C. Glaeser, Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing, Proceedings of the 14th annual workshop on Microprogramming, 1981.
DOI : 10.1145/1014192.802449

B. Rau, M. Lee, P. Tirumalai, and M. Schlansker, Register allocation for software pipelined loops, Proceedings PLDI'92, 1992.

J. Rushby, Bus Architectures for Safety-Critical Embedded Systems, Proceedings EM- SOFT'01, 2001.
DOI : 10.1007/3-540-45449-7_22

M. Smelyanskyi, S. Mahlke, E. Davidson, and H. Lee, Predicate-aware scheduling: a technique for reducing resource constraints, International Symposium on Code Generation and Optimization, 2003. CGO 2003., 2003.
DOI : 10.1109/CGO.2003.1191543

J. Wang and C. Eisenbeis, Decomposed software pipelining, 1993.
URL : https://hal.archives-ouvertes.fr/inria-00074834

D. M. Warter, W. Lavery, and . Hwu, The benefit of predicated execution for software pipelining, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences, 1993.
DOI : 10.1109/HICSS.1993.283949

H. Yang and S. Ha, Pipelined data parallel task mapping/scheduling technique for mpsoc, Design, Automation Test in Europe Conference Exhibition (DATE), 2009.

H. Yun, J. Kim, and S. Moon, Time optimal software pipelining of loops with control flows, International Journal of Parallel Programming, issue.5, pp.31339-391, 2003.

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, Register constrained modulo scheduling. Parallel and Distributed Systems, IEEE Transactions on, vol.15, issue.5, pp.417-430, 2004.
DOI : 10.1109/tpds.2004.1278099
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.231.6

W. Zheng, J. Chong, C. Pinello, S. Kanajan, and A. Sangiovanni-vincentelli, Extensible and scalable time triggered scheduling, Fifth International Conference on Application of Concurrency to System Design (ACSD'05), 2005.
DOI : 10.1109/ACSD.2005.13

Q. Zhuge, Z. Shao, and E. Sha, Optimal code size reduction for software-pipelined loops on dsp applications, Proceedings of the International Conference on Parallel Processing, 2002.