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FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions

Abstract : Partial dynamic reconfiguration has become an important feature of FPGA-based systems as the number of applications which use this capability has increased. For systems using multiple partial bitstreams, the complexity of the target reconfigurable region, which often include heterogeneous blocks such as block RAMs and DSP blocks, makes it difficult to generate a unique bitstream which can be loaded into multiple locations in an FPGA. Although the migration of homogeneous lookup-table based logic blocks across the logic fabric has been shown to be relatively straightforward for older FPGAs, the variety and organization of heterogeneous blocks in modern FPGAs now render this operation more complex. In many applications, it is desirable to place and route a partial design once, store it in memory, and then freely load it into the reconfigurable fabric with as few constraints as possible. This work addresses the need to relocate partial designs which include heterogeneous resources.
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https://hal.inria.fr/hal-01100334
Contributor : Christophe Huriaux Connect in order to contact the contributor
Submitted on : Tuesday, April 7, 2015 - 3:16:34 PM
Last modification on : Tuesday, October 19, 2021 - 11:58:52 PM

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Christophe Huriaux, Olivier Sentieys, Russell Tessier. FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions. FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, United States. pp.30, ⟨10.1109/FCCM.2014.17⟩. ⟨hal-01100334⟩

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