Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters, International Symposium on Code Generation and Optimization, 2005. ,
DOI : 10.1109/CGO.2005.14
Virtual-Machine Abstraction and Optimization Techniques, Electronic Notes in Theoretical Computer Science, vol.253, issue.5, pp.3-14, 2009. ,
DOI : 10.1016/j.entcs.2009.11.011
URL : http://doi.org/10.1016/j.entcs.2009.11.011
Target prediction for indirect jumps, ISCA, 1997. ,
CLI back-end in GCC, GCC Developers' Summit, 2007. ,
Compiling Java just in time, IEEE Micro, vol.17, issue.3, p.17, 1997. ,
DOI : 10.1109/40.591653
Cint: a RISC interpreter for the C programming language, Symposium on Interpreters and interpretive techniques, 1987. ,
Accurate indirect branch prediction, ISCA, 1998. ,
DOI : 10.1109/isca.1998.694772
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.2734
The Dalvik virtual machine architecture, 2010. ,
Stack caching for interpreters, PLDI, 1995. ,
The Behavior of Efficient Virtual Machine Interpreters on Modern Architectures, EuroPar, 2001. ,
DOI : 10.1007/3-540-44681-8_59
Optimizing indirect branch prediction accuracy in virtual machine interpreters, PLDI, 2003. ,
Combining stack caching with dynamic superinstructions, Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators , IVME '04, 2004. ,
DOI : 10.1145/1059579.1059583
Intel 64 and IA-32 Architectures Software Developer's Manual, 2013. ,
Dynamic branch prediction with perceptrons, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001. ,
DOI : 10.1109/HPCA.2001.903263
The bi-mode branch predictor, MICRO, 1997. ,
Pin: building customized program analysis tools with dynamic instrumentation How to tune applications using a top-down characterization of microarchitectural issues, PLDI, 2005. [18] J. Marusarz, S. Cepeda, and A. Yasin ,
Compiler techniques to improve dynamic branch prediction for indirect jump and call instructions, ACM Transactions on Architecture and Code Optimization, vol.8, issue.4, p.2012 ,
DOI : 10.1145/2086696.2086703
Combining branch predictors, 1993. ,
Trading conflict and capacity aliasing in conditional branch predictors, SIGARCH Comput. Archit. News, vol.25, issue.2, 1997. ,
The role of interpreters in high performance computing, ACAT in Physics Research, 2008. ,
Optimizing direct threaded code by selective inlining, SIGPLAN Not, vol.33, issue.5, 1998. ,
An analysis of the dynamic behavior of JavaScript programs, PLDI, 2010. ,
Tiptop: Hardware Performance Counters for the Masses, 2012 41st International Conference on Parallel Processing Workshops, 2011. ,
DOI : 10.1109/ICPPW.2012.58
URL : https://hal.archives-ouvertes.fr/hal-00639173
Efficient interpreter optimizations for the JVM, Proceedings of the 2013 International Conference on Principles and Practices of Programming on the Java Platform Virtual Machines, Languages, and Tools, PPPJ '13, 2013. ,
DOI : 10.1145/2500828.2500839
Analysis of the O-GEometric History Length Branch Predictor, ISCA, 2005. ,
A new case for the TAGE branch predictor, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, 2011. ,
DOI : 10.1145/2155620.2155635
URL : https://hal.archives-ouvertes.fr/hal-00639193
Design tradeoffs for the alpha EV8 conditional branch predictor, Proceedings 29th Annual International Symposium on Computer Architecture, 2002. ,
DOI : 10.1109/ISCA.2002.1003587
A case for (partially) TAgged GEometric history length branch prediction, JILP, vol.8, 2006. ,
Virtual machine showdown: Stack versus registers, ACM TACO, vol.4, issue.4, 2008. ,
DOI : 10.1145/1328195.1328197
The agree predictor: A mechanism for reducing negative branch history interference, ISCA, 1997. ,
Catenation and specialization for Tcl virtual machine performance, Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators , IVME '04, 2004. ,
DOI : 10.1145/1059579.1059591
Can hardware performance counters produce expected, deterministic results? In FHPM, 2010. ,
Two-level adaptive training branch prediction, Proceedings of the 24th annual international symposium on Microarchitecture , MICRO 24, 1991. ,
DOI : 10.1145/123465.123475