M. Berndl, B. Vitale, M. Zaleski, and A. D. Brown, Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters, International Symposium on Code Generation and Optimization, 2005.
DOI : 10.1109/CGO.2005.14

S. Brunthaler, Virtual-Machine Abstraction and Optimization Techniques, Electronic Notes in Theoretical Computer Science, vol.253, issue.5, pp.3-14, 2009.
DOI : 10.1016/j.entcs.2009.11.011
URL : http://doi.org/10.1016/j.entcs.2009.11.011

P. Chang, E. Hao, and Y. N. Patt, Target prediction for indirect jumps, ISCA, 1997.

R. Costa, A. C. Ornstein, and E. Rohou, CLI back-end in GCC, GCC Developers' Summit, 2007.

T. Cramer, R. Friedman, T. Miller, D. Seberger, R. Wilson et al., Compiling Java just in time, IEEE Micro, vol.17, issue.3, p.17, 1997.
DOI : 10.1109/40.591653

J. W. Davidson and J. V. Gresh, Cint: a RISC interpreter for the C programming language, Symposium on Interpreters and interpretive techniques, 1987.

K. Driesen and U. Hölzle, Accurate indirect branch prediction, ISCA, 1998.
DOI : 10.1109/isca.1998.694772
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.2734

D. Ehringer, The Dalvik virtual machine architecture, 2010.

M. A. Ertl, Stack caching for interpreters, PLDI, 1995.

M. A. Ertl and D. Gregg, The Behavior of Efficient Virtual Machine Interpreters on Modern Architectures, EuroPar, 2001.
DOI : 10.1007/3-540-44681-8_59

M. A. Ertl and D. Gregg, Optimizing indirect branch prediction accuracy in virtual machine interpreters, PLDI, 2003.

M. A. Ertl and D. Gregg, Combining stack caching with dynamic superinstructions, Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators , IVME '04, 2004.
DOI : 10.1145/1059579.1059583

. Intel, Intel 64 and IA-32 Architectures Software Developer's Manual, 2013.

D. A. Jiménez and C. Lin, Dynamic branch prediction with perceptrons, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001.
DOI : 10.1109/HPCA.2001.903263

C. Lee, I. K. Chen, and T. N. Mudge, The bi-mode branch predictor, MICRO, 1997.

C. Luk, Pin: building customized program analysis tools with dynamic instrumentation How to tune applications using a top-down characterization of microarchitectural issues, PLDI, 2005. [18] J. Marusarz, S. Cepeda, and A. Yasin

J. Mccandless and D. Gregg, Compiler techniques to improve dynamic branch prediction for indirect jump and call instructions, ACM Transactions on Architecture and Code Optimization, vol.8, issue.4, p.2012
DOI : 10.1145/2086696.2086703

S. Mcfarling, Combining branch predictors, 1993.

P. Michaud, A. Seznec, and R. Uhlig, Trading conflict and capacity aliasing in conditional branch predictors, SIGARCH Comput. Archit. News, vol.25, issue.2, 1997.

A. Naumann and P. Canal, The role of interpreters in high performance computing, ACAT in Physics Research, 2008.

I. Piumarta and F. Riccardi, Optimizing direct threaded code by selective inlining, SIGPLAN Not, vol.33, issue.5, 1998.

G. Richards, S. Lebresne, B. Burg, and J. Vitek, An analysis of the dynamic behavior of JavaScript programs, PLDI, 2010.

E. Rohou, Tiptop: Hardware Performance Counters for the Masses, 2012 41st International Conference on Parallel Processing Workshops, 2011.
DOI : 10.1109/ICPPW.2012.58
URL : https://hal.archives-ouvertes.fr/hal-00639173

G. Savrun-yeniçeri, Efficient interpreter optimizations for the JVM, Proceedings of the 2013 International Conference on Principles and Practices of Programming on the Java Platform Virtual Machines, Languages, and Tools, PPPJ '13, 2013.
DOI : 10.1145/2500828.2500839

A. Seznec, Analysis of the O-GEometric History Length Branch Predictor, ISCA, 2005.

A. Seznec, A new case for the TAGE branch predictor, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, 2011.
DOI : 10.1145/2155620.2155635
URL : https://hal.archives-ouvertes.fr/hal-00639193

A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides, Design tradeoffs for the alpha EV8 conditional branch predictor, Proceedings 29th Annual International Symposium on Computer Architecture, 2002.
DOI : 10.1109/ISCA.2002.1003587

A. Seznec and P. Michaud, A case for (partially) TAgged GEometric history length branch prediction, JILP, vol.8, 2006.

Y. Shi, K. Casey, M. A. Ertl, and D. Gregg, Virtual machine showdown: Stack versus registers, ACM TACO, vol.4, issue.4, 2008.
DOI : 10.1145/1328195.1328197

E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt, The agree predictor: A mechanism for reducing negative branch history interference, ISCA, 1997.

B. Vitale and T. S. Abdelrahman, Catenation and specialization for Tcl virtual machine performance, Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators , IVME '04, 2004.
DOI : 10.1145/1059579.1059591

V. M. Weaver and J. Dongarra, Can hardware performance counters produce expected, deterministic results? In FHPM, 2010.

T. Yeh and Y. N. Patt, Two-level adaptive training branch prediction, Proceedings of the 24th annual international symposium on Microarchitecture , MICRO 24, 1991.
DOI : 10.1145/123465.123475