Synchronising C/C++ and POWER

Abstract : Shared memory concurrency relies on synchronisation primitives: compare-and-swap, load-reserve/store-conditional (aka LL/SC), language-level mutexes, and so on. In a sequentially consistent setting, or even in the TSO setting of x86 and Sparc, these have well-understood semantics. But in the very relaxed settings of IBM POWER , ARM, or C/C++, it remains surprisingly unclear exactly what the programmer can depend on. This paper studies relaxed-memory synchronisation. On the hardware side, we give a clear semantic characterisation of the load-reserve/store-conditional primitives as provided by POWER multiprocessors, for the first time since they were introduced 20 years ago; we cover their interaction with relaxed loads, stores, barriers, and dependencies. Our model, while not officially sanc-tioned by the vendor, is validated by extensive testing, comparing actual implementation behaviour against an oracle generated from the model, and by detailed discussion with IBM staff. We believe the ARM semantics to be similar. On the software side, we prove sound a proposed compilation scheme of the C/C++ synchronisation constructs to POWER, in-cluding C/C++ spinlock mutexes, fences, and read-modify-write operations, together with the simpler atomic operations for which soundness is already known from our previous work; this is a first step in verifying concurrent algorithms that use load-reserve/store-conditional with respect to a realistic semantics. We also build con-fidence in the C/C++ model in its own terms, fixing some omis-sions and contributing to the C standards committee adoption of the C++11 concurrency model.
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Susmit Sarkar, Kayvan Memarian, Scott Owens, Mark Batty, Peter Sewell, et al.. Synchronising C/C++ and POWER. PLDI '12: Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun 2012, Beijing, China. ⟨10.1145/2254064.2254102⟩. ⟨hal-01100798⟩

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