3D Hardware Canaries

Abstract : 3D integration is a promising advanced manufacturing process offering a variety of new hardware security protection opportunities. This paper presents a way of securing 3D ICs using Hamiltonian paths as hardware integrity verification sensors. As 3D integration consists in the stacking of many metal layers, one can consider surrounding a security-sensitive circuit part by a wire cage. After exploring and comparing different cage construction strategies (and reporting preliminary implementation results on silicon), we introduce a ”hardware canary”. The canary is a spatially distributed chain of functions F i positioned at the vertices of a 3D cage surrounding a protected circuit. A correct answer (F n  ∘ … ∘ F 1)(m) to a challenge m attests the canary’s integrity
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Communication dans un congrès
Emmanuel Prouff; Patrick Schaumont. CHES 2012 - 14th International Workshop Cryptographic Hardware and Embedded Systems, Sep 2012, Leuven, Belgium. Springer, LNCS - Lecture Notes in Computer Science, 7428, pp.1-22, 2012, Cryptographic Hardware and Embedded Systems – CHES 2012. 〈10.1007/978-3-642-33027-8_1〉
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https://hal.inria.fr/hal-01111533
Contributeur : Brigitte Briot <>
Soumis le : vendredi 30 janvier 2015 - 15:07:06
Dernière modification le : vendredi 25 mai 2018 - 12:02:05

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Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, et al.. 3D Hardware Canaries. Emmanuel Prouff; Patrick Schaumont. CHES 2012 - 14th International Workshop Cryptographic Hardware and Embedded Systems, Sep 2012, Leuven, Belgium. Springer, LNCS - Lecture Notes in Computer Science, 7428, pp.1-22, 2012, Cryptographic Hardware and Embedded Systems – CHES 2012. 〈10.1007/978-3-642-33027-8_1〉. 〈hal-01111533〉

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