Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors
Résumé
We propose a software-based approach using dynamic voltage overscaling to reduce the energy consumption of HPC applications. This technique aggressively lowers the supply voltage below nominal voltage, which introduces timing errors, and we use ABFT to provide fault tolerance for matrix operations. We introduce a formal model for and design optimal polynomial-time solutions to execute a linear chain of tasks. Simulation results obtained for matrix multiplication demonstrate that our approach indeed leads to significant energy savings, compared to the standard algorithm that always operates at nominal voltage.
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