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High performance Discrete Cosine Transform (DCT) operator using multimedia oriented subword parallelism (SWP)

Shafqat Khan 1 Emmanuel Casseau 1 Daniel Menard 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Keywords : data level parallelism multimedia processing discrete cosine transform subword parallelism reconfigurable system embedded system
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https://hal.inria.fr/hal-01121890
Contributor : Emmanuel Casseau <>
Submitted on : Monday, March 2, 2015 - 5:14:16 PM
Last modification on : Friday, July 10, 2020 - 4:26:04 PM

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UNIV-RENNES1 | CNRS | INRIA | IRISA | IRISA-D3 | INSTITUT-TELECOM | UR1-UFR-ISTIC | CENTRALESUPELEC | UNIV-RENNES | INSA-RENNES

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Shafqat Khan, Emmanuel Casseau, Daniel Menard. High performance Discrete Cosine Transform (DCT) operator using multimedia oriented subword parallelism (SWP). Advances in Computer Engineering, Hindawi, 2015, Advances in Computer Engineering, 2015, pp.10. ⟨10.1155/2015/405856⟩. ⟨hal-01121890⟩

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