Towards Modeling and Simulation of Exascale Computing Platforms

Luka Stanisic 1, 2
2 MESCAL - Middleware efficiently scalable
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : Future super-computer platforms will be facing big challenges due to the enormous power consumption. One possible solution to this problem would be to develop HPC systems from today’s energy-efficient hardware solutions used in embedded and mobile devices like ARM. However, ARM chips have never been used in HPC programing before, leading to a number of significant challenges. Therefore, we experimented with ARM processors and compared their performance with the architectures that are known better, in this case last generations of Intel processors. Due to the memory bottleneck of most scientific applications, understanding the performance of CPU caches in this context is crucial, thus this research was investigat- ing the processor performance depending on memory hierarchy. We present not only differences and complexity of these two architectures, but also how changing seemingly innocuous aspects of an experimental setup can cause completely distinctive behavior. Additionally, we demonstrate very clean and systematic methodology, which aid us in achieving good performance estimations.
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Mémoires d'étudiants -- Hal-inria+
Distributed, Parallel, and Cluster Computing [cs.DC]. 2012
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Contributeur : Luka Stanisic <>
Soumis le : mercredi 11 mai 2016 - 11:24:05
Dernière modification le : mercredi 11 avril 2018 - 01:53:06
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Luka Stanisic. Towards Modeling and Simulation of Exascale Computing Platforms. Distributed, Parallel, and Cluster Computing [cs.DC]. 2012. 〈hal-01158585〉

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