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Data-aware Process Networks

Christophe Alias 1, * Alexandru Plesco 1 
* Corresponding author
1 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : This report presents the Data-aware Process Networks, a new parallel execution model adapted to the hardware constraints of high-level synthesis, where the data transferts are made explicit. We show that the DPN model is consistant in the meaning where any translation of a sequential program produces an equivalent DPN without deadlocks. Finally, we show how to compile a sequential program to a DPN and how to optimize the input/output and the parallelism.
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Submitted on : Monday, June 1, 2015 - 6:46:05 PM
Last modification on : Wednesday, October 26, 2022 - 8:15:40 AM
Long-term archiving on: : Monday, April 24, 2017 - 9:11:24 PM


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  • HAL Id : hal-01158726, version 1


Christophe Alias, Alexandru Plesco. Data-aware Process Networks. [Rapport de recherche] RR-8735, Inria - Research Centre Grenoble – Rhône-Alpes; INRIA. 2015, pp.32. ⟨hal-01158726⟩



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