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Full Hardware Implementation of Short Addition Chains Recoding for ECC Scalar Multiplication

Abstract : Ensuring uniform computation profiles is an efficient protection against some side channel attacks (SCA) in embedded systems. Typical elliptic curve cryptography (ECC) scalar multiplication methods use two point operations (addition and doubling) scheduled according to secret scalar digits. Euclidean addition chains (EAC) offer a natural SCA protection since only one point operation is used. Computing short EACs is considered as a very costly operation and no hardware implementation has been reported yet. We designed an hardware recoding unit for short EACs which works concurrently to scalar multiplication. It has been integrated in an in-house ECC processor on various FPGAs. The implementation results show similar computation times compared to non-protected solutions, and faster ones compared to typical protected solutions (e. g. 18 % speed-up over 192 b Montgomery ladder).
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Contributor : Arnaud TISSERAND Connect in order to contact the contributor
Submitted on : Thursday, July 2, 2015 - 6:45:51 PM
Last modification on : Thursday, January 20, 2022 - 4:13:18 PM
Long-term archiving on: : Tuesday, April 25, 2017 - 10:19:28 PM


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  • HAL Id : hal-01171095, version 1


Julien Proy, Nicolas Veyrat-Charvillon, Arnaud Tisserand, Nicolas Méloni. Full Hardware Implementation of Short Addition Chains Recoding for ECC Scalar Multiplication. Compas: Conférence d’informatique en Parallélisme, Architecture et Système, Jun 2015, Lille, France. ⟨hal-01171095⟩



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