]. P. Burgio, Core Platforms with Shared Memory Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis MORPHEUS: Heterogeneous Reconfigurable Computing, " in Field Programmable Logic and Applications (FPL) Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor Morphable hundred-core heterogeneous architecture for energy-aware computation EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile SystemsCoMik: A predictable and cycle-accurately composable real-time microkernel, 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC), 2014. [3] F. Thoma und et Design, Automation and Test in Europe (DATE) Parallel and Distributed Processing with Applications (ISPA) Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.49-62, 2007.

A. Nieuwland, C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems Adaptive multiprocessor systems-on-chip architectures: Principles, methods and tools, Design Automation for Embedded Systems, vol.7, issue.3, pp.233-270, 2002.
DOI : 10.1023/A:1019782306621

K. Goossens, J. Dielissen, and A. Radulescu, ??thereal Network on Chip:Concepts, Architectures, and Implementations, IEEE Design and Test of Computers, vol.22, issue.5, pp.414-421, 2005.
DOI : 10.1109/MDT.2005.99

R. Brillu, Accelerator Interface, a keystone for heterogenous "MPSoC" architectures, Design, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00808400

C. Huriaux, Design Flow and Run-Time Management for Compressed FPGA Configurations, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015.
DOI : 10.7873/DATE.2015.1007
URL : https://hal.archives-ouvertes.fr/hal-01089319

M. Barreteau, R. Barrère, and E. Lenormand, Programming GPUs from High Level Data Flow Models, Patterns for Parallel Programming on GPUs, F. Magoulès, pp.73-108, 2014.
DOI : 10.4203/csets.34.4

A. Demeure and Y. D. Gallo, Array-OL: An Approach for Signal Processing Design, SAME, System On Chip session, 1998.

J. Rose, The VTR project, Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA '12, 2012.
DOI : 10.1145/2145694.2145708

S. M. Smith and J. M. Bradley, SUSAN?A New Approach to Low Level Image Processing, International Journal of Computer Vision, vol.23, issue.1, pp.45-78, 1997.
DOI : 10.1023/A:1007963824710