M. Advanced and . Devices, AMD K6-III Processor Data Sheet, pp.11-12, 1998.

R. Bhargava and L. K. John, Latency and energy aware value prediction for high-frequency processors, Proceedings of the 16th international conference on Supercomputing , ICS '02, pp.45-56, 2002.
DOI : 10.1145/514191.514201

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi et al., The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011.
DOI : 10.1145/2024716.2024718

M. Burtscher, Improving context-based load value prediction, 2000.

M. Burtscher and B. G. Zorn, Hybridizing and coalescing load value predictors, Proceedings 2000 International Conference on Computer Design, pp.81-92, 2000.
DOI : 10.1109/ICCD.2000.878272
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.8084

G. Z. Chrysos and J. S. Emer, Memory dependence prediction using store sets, Proceedings of the International Symposium on Computer Architecture, pp.142-153, 1998.
DOI : 10.1109/isca.1998.694770
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.6285

R. Eickemeyer and S. Vassiliadis, A load-instruction unit for pipelined processors, IBM Journal of Research and Development, vol.37, issue.4, pp.547-564, 1993.
DOI : 10.1147/rd.374.0547

D. Ernst and T. Austin, Efficient dynamic scheduling through tag elimination, Proceedings of the International Symposium on Computer Architecture, pp.37-46, 2002.
DOI : 10.1145/545214.545221
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.106.7152

B. Fahs, T. Rafacz, S. J. Patel, and S. S. Lumetta, Continuous optimization, 32nd International Symposium on Computer Architecture (ISCA'05), pp.86-97, 2005.
DOI : 10.1109/ISCA.2005.19

F. Gabbay and A. Mendelson, The effect of instruction fetch bandwidth on value prediction, Proceedings of The International Symposium on Computer Architecture, pp.272-281, 1998.

F. Gabbay and A. Mendelson, Using value prediction to increase the power of speculative execution hardware, ACM Transactions on Computer Systems, vol.16, issue.3, pp.234-270, 1998.
DOI : 10.1145/290409.290411

S. Gochman, R. Ronen, I. Anati, A. Berkovits, T. Kurts et al., The Intel Pentium M processor: Microarchitecture and performance, Intel Technology Journal, vol.7, 2003.

B. Goeman, H. Vandierendonck, and K. De-bosschere, Differential FCM: increasing value prediction accuracy by improving table usage efficiency, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, pp.207-216, 2001.
DOI : 10.1109/HPCA.2001.903264

M. Golden, S. Arekapudi, and J. Vinh, 40-entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86 64 core, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.80-82, 2011.

S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp.216-225, 1998.
DOI : 10.1109/MICRO.1998.742783

I. Kim and M. H. Lipasti, Half-price architecture, Proceedings of the International Symposium on Computer Architecture, pp.28-38, 2003.
DOI : 10.1145/859618.859623
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.13.2939

S. Lee, Y. Wang, and P. Yew, Decoupled value prediction on trace processors, Proceedings of the International Symposium on High-Performance Computer Architecture, pp.231-240, 2000.

S. Lee and P. Yew, On table bandwidth and its update delay for value prediction on wide-issue ilp processors, IEEE Transactions on, vol.50, issue.8, pp.847-852, 2001.

M. H. Lipasti and J. P. Shen, Exceeding the dataflow limit via value prediction, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29, pp.226-237, 1996.
DOI : 10.1109/MICRO.1996.566464

M. Lipasti, C. Wilkerson, and J. Shen, Value locality and load value prediction, 1996.
DOI : 10.1145/237090.237173
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.122.8305

G. H. Loh, Width prediction for reducing value predictor size and power, First Value Prediction Workshop, ISCA, 2003.

A. Mendelson and F. Gabbay, Speculative execution based on value prediction, 1997.

T. Nakra, R. Gupta, and M. Soffa, Global context-based value prediction, Proceedings Fifth International Symposium on High-Performance Computer Architecture, pp.4-12, 1999.
DOI : 10.1109/HPCA.1999.744311
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.363.9188

S. Palacharla, N. Jouppi, and J. Smith, Complexity-effective superscalar processors, Proceedings of the International Symposium on Computer Architecture, pp.206-218, 1997.
DOI : 10.1145/384286.264201
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.527.5571

A. Perais and A. Seznec, EOLE, Proceedings of the International Symposium on Computer Architecture, 2014.
DOI : 10.1145/2678373.2665742
URL : https://hal.archives-ouvertes.fr/hal-01193287

A. Perais and A. Seznec, Practical data value speculation for future high-end processors, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014.
DOI : 10.1109/HPCA.2014.6835952
URL : https://hal.archives-ouvertes.fr/hal-01088116

E. Perelman, G. Hamerly, and B. Calder, Picking statistically valid and early simulation points, Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362), p.244, 2003.
DOI : 10.1109/PACT.2003.1238020
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.6.1240

V. Petric, T. Sha, and A. Roth, RENO: a rename-based instruction optimizer, 32nd International Symposium on Computer Architecture (ISCA'05), pp.98-109, 2005.
DOI : 10.1109/ISCA.2005.43

B. Rychlik, J. Faistl, B. Krug, A. Kurland, J. Sung et al., Efficient and accurate value prediction using dynamic classification, 1998.

T. Sato and I. Arita, Table size reduction for data value predictors by exploiting narrow width values, Proceedings of the 14th international conference on Supercomputing , ICS '00, pp.196-205, 2000.
DOI : 10.1145/335231.335250

T. Sato and I. Arita, Low-Cost Value Predictors Using Frequent Value Locality, High Performance Computing, pp.106-119, 2002.
DOI : 10.1007/3-540-47847-7_11

Y. Sazeides and J. Smith, The predictability of data values, Proceedings of 30th Annual International Symposium on Microarchitecture, pp.248-258, 1997.
DOI : 10.1109/MICRO.1997.645815

Y. Sazeides and J. Smith, Implementations of context based value predictors, 1998.

A. Seznec, A new case for the TAGE branch predictor, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, pp.117-127, 2011.
DOI : 10.1145/2155620.2155635
URL : https://hal.archives-ouvertes.fr/hal-00639193

A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides, Design tradeoffs for the alpha EV8 conditional branch predictor, Proceedings of the Interational Symoposiumy on Computer Architecture, pp.295-306, 2002.

A. Seznec and P. Michaud, A case for (partially) TAgged GEometric history length branch prediction, Journal of Instruction Level Parallelism, vol.8, pp.1-23, 2006.