J. Bajard, L. Didier, and P. Kornerup, An RNS Montgomery modular multiplication algorithm, IEEE Transactions on Computers, vol.47, issue.7, pp.766-776, 1998.
DOI : 10.1109/12.709376

J. Bajard, L. Didier, and P. Kornerup, Modular multiplication and base extensions in residue number systems, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.59-65, 2001.
DOI : 10.1109/ARITH.2001.930104

J. Bajard, S. Duquesne, and M. D. Ercegovac, Combining leak-resistant arithmetic for elliptic curves defined over Fp and RNS representation, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01098795

J. Bajard, J. Eynard, and F. Gandino, Fault Detection in RNS Montgomery Modular Multiplication, 2013 IEEE 21st Symposium on Computer Arithmetic, pp.119-126, 2013.
DOI : 10.1109/ARITH.2013.31

URL : https://hal.archives-ouvertes.fr/hal-01065507

J. Bajard, J. Eynard, N. Merkiche, and T. Plantard, Baba¨?Baba¨? round-off CVP method in RNS: Application to lattice based cryptographic protocols, Proc. 14th International Symposium on Integrated Circuits (ISIC), pp.440-443, 2014.

J. Bajard, L. Imbert, P. Liardet, and Y. Teglia, Leak Resistant Arithmetic, Proc. Cryptographic Hardware and Embedded Systems (CHES), pp.62-75, 2004.
DOI : 10.1007/978-3-540-28632-5_5

URL : https://hal.archives-ouvertes.fr/lirmm-00108863

J. Bajard, M. Kaihara, and T. Plantard, Selected RNS Bases for Modular Multiplication, 2009 19th IEEE Symposium on Computer Arithmetic, pp.25-32, 2009.
DOI : 10.1109/ARITH.2009.20

URL : https://hal.archives-ouvertes.fr/lirmm-00394985

J. Bajard and N. Merkiche, Double Level Montgomery Cox-Rower Architecture, New Bounds, Proc. 13th Smart Card Research and Advanced Application Conference (CARDIS), 2014.
DOI : 10.1007/978-3-319-16763-3_9

URL : https://hal.archives-ouvertes.fr/hal-01098803

K. Bigou and A. Tisserand, RNS modular multiplication through reduced base extensions, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, pp.57-62, 2014.
DOI : 10.1109/ASAP.2014.6868631

URL : https://hal.archives-ouvertes.fr/hal-01010961

R. C. Cheung, S. Duquesne, J. Fan, N. Guillermin, I. Verbauwhede et al., FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction, Proc. Cryptographic Hardware and Embedded Systems (CHES), pp.421-441, 2011.
DOI : 10.1007/978-3-642-23951-9_28

URL : https://hal.archives-ouvertes.fr/hal-00745016

M. Esmaeildoust, D. Schinianakis, H. Javashi, T. Stouraitis, and K. Navi, Efficient RNS implementation of elliptic curve point multiplication over GF(p), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1545-1549, 2013.

F. Gandino, F. Lamberti, G. Paravati, J. Bajard, and P. Montuschi, An Algorithmic and Architectural Study on Montgomery Exponentiation in RNS, IEEE Transactions on Computers, vol.61, issue.8, pp.611071-1083, 2012.
DOI : 10.1109/TC.2012.84

URL : https://hal.archives-ouvertes.fr/hal-01098799

H. L. Garner, The residue number system, IRE Transactions on Electronic Computers, issue.82, pp.140-147, 1959.

N. Guillermin, A high speed coprocessor for elliptic curve scalar multiplications over Fp, Proc. Cryptographic Hardware and Embedded Systems (CHES), pp.48-64, 2010.

N. Guillermin, A coprocessor for secure and high speed modular arithmetic, 2011.

M. Joye and S. Yen, The Montgomery Powering Ladder, Proc. 4th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.291-302, 2002.
DOI : 10.1007/3-540-36400-5_22

A. Karatsuba and Y. Ofman, Multiplication of multi-digit numbers on automata. Doklady Akad, Translation in Soviet Physics- Doklady, pp.293-294, 1962.

S. Kawamura, M. Koike, F. Sano, and A. Shimbo, Cox-Rower Architecture for Fast Parallel Montgomery Multiplication, Proc. 19th International Conference on the Theory and Application of Cryptographic (EUROCRYPT), volume 1807 of LNCS, pp.523-538, 2000.
DOI : 10.1007/3-540-45539-6_37

S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards, 2007.

P. L. Montgomery, Modular multiplication without trial division, Mathematics of Computation, vol.44, issue.170, pp.519-521, 1985.
DOI : 10.1090/S0025-5718-1985-0777282-X

H. Nozaki, M. Motoyama, A. Shimbo, and S. Kawamura, Implementation of RSA Algorithm Based on RNS Montgomery Multiplication, Proc. Cryptographic Hardware and Embedded Systems (CHES), pp.364-376, 2001.
DOI : 10.1007/3-540-44709-1_30

G. Perin, L. Imbert, L. Torres, and P. Maurine, Electromagnetic Analysis on RSA Algorithm Based on RNS, 2013 Euromicro Conference on Digital System Design, pp.345-352, 2013.
DOI : 10.1109/DSD.2013.44

URL : https://hal.archives-ouvertes.fr/lirmm-00861215

B. J. Phillips, Y. Kong, and Z. Lim, Highly parallel modular multiplication in the residue number system using sum of residues reduction, Applicable Algebra in Engineering, Communication and Computing, vol.21, issue.2, pp.249-255, 2010.
DOI : 10.1007/s00200-010-0124-2

K. C. Posch and R. Posch, Basiserweiterung mit einer Konvolutionssumme in Restklassenzahlensystemen, Computing, vol.17, issue.2, pp.93-104, 1993.
DOI : 10.1007/BF02238608

K. C. Posch and R. Posch, Modulo reduction in residue number systems, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.5, pp.449-454, 1995.
DOI : 10.1109/71.382314

D. Schinianakis and T. Stouraitis, An RNS barrett modular multiplication architecture, 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2229-2232, 2014.
DOI : 10.1109/ISCAS.2014.6865613

A. P. Shenoy and R. Kumaresan, Fast base extension using a redundant modulus in RNS, IEEE Transactions on Computers, vol.38, issue.2, pp.292-297, 1989.
DOI : 10.1109/12.16508

A. Svoboda and M. Valach, Operátorové obvody (operator circuits in czech), Stroje na Zpracování Informací (Information Processing Machines), pp.247-296, 1955.

N. S. Szabo and R. I. Tanaka, Residue arithmetic and its applications to computer technology, 1967.

R. Szerwinski and T. Guneysu, Exploiting the Power of GPUs for Asymmetric Cryptography, Proc. 10th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.79-99, 2008.
DOI : 10.1007/978-3-540-85053-3_6

G. X. Yao, J. Fan, R. C. Cheung, and I. Verbauwhede, Faster Pairing Coprocessor Architecture, Proc. 5th Pairing-Based Cryptography (Pairing), pp.160-176, 2012.
DOI : 10.1007/978-3-642-36334-4_10