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Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors

Abstract : We propose a software-based approach using dynamic voltage overscaling to reduce the energy consumption of HPC applications. This technique aggressively lowers the supply voltage below nominal voltage, which introduces timing errors , and we use Algorithm-Based Fault-Tolerance (ABFT) to provide fault tolerance for matrix operations. We introduce a formal model, and we design optimal polynomial-time solutions, to execute a linear chain of tasks. Evaluation results obtained for matrix multiplication demonstrate that our approach indeed leads to significant energy savings, compared to the standard algorithm that always operates at nominal voltage.
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https://hal.inria.fr/hal-01199250
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Submitted on : Friday, September 25, 2015 - 11:35:54 AM
Last modification on : Tuesday, November 19, 2019 - 2:39:39 AM
Long-term archiving on: : Tuesday, December 29, 2015 - 7:03:25 AM

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Aurélien Cavelan, Yves Robert, Hongyang Sun, Frédéric Vivien. Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors. FTXS '15: 5th Workshop on Fault Tolerance for HPC at eXtreme Scale, Jun 2015, Portland, United States. pp.8, ⟨10.1145/2751504.2751508⟩. ⟨hal-01199250⟩

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