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Hardware Accelerators for ECC and HECC

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Abstract

Elliptic curve cryptography (ECC) is the current main standard for asymmetric cryptography. Hyper-elliptic curve cryptography (HECC) is investigated for future applications. Our research group studies and prototypes hardware accelerators for ECC and HECC. Our accelerator architecture can be customized at design time with various numbers and types of units, curves parameters, key recoding methods and embedded protections against physical attacks (both passive and active ones). Finite field operations are handled in dedicated hardware units. Curve level operations (e.g. point addition and doubling) are handled in software using an instruction memory programmable by users at run time. Various configurations of the accelerator can be generated for very lost cost solutions up to fast but costly ones. Various protections can be added such as randomized key recoding schemes, arithmetic units with uniform power profiles, randomized internal memory accesses. We also develop a complete software tool chain to program our accelerator (from assembly level to Python code inside Sage). Some configurations of our accelerator, and the corresponding software tools, will be available for academic and industrial collaborations. In this talk, we will present our architecture, our tool chain, several configurations of the arithmetic units and the impact of various protections. Our current results in mid-range FPGAs show that HECC leads to 40% more efficient solutions than ECC for a similar security level and silicon cost.
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Dates and versions

hal-01207422 , version 1 (30-09-2015)

Identifiers

  • HAL Id : hal-01207422 , version 1

Cite

Arnaud Tisserand. Hardware Accelerators for ECC and HECC. ECC: 19th Workshop on Elliptic Curve Cryptography, Sep 2015, Bordeaux, France. ⟨hal-01207422⟩
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