T. Chabrier, D. Pamula, and A. Tisserand, Hardware implementation of DBNS recoding for ECC processor, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers
DOI : 10.1109/ACSSC.2010.5757580

URL : https://hal.archives-ouvertes.fr/inria-00536587

Y. Ma, Z. Liu, W. Pan, and J. Jing, A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$
DOI : 10.1007/978-3-662-43414-7_21

D. Pamula and A. Tisserand, Fast and Secure Finite Field Multipliers, 2015 Euromicro Conference on Digital System Design
DOI : 10.1109/DSD.2015.46

URL : https://hal.archives-ouvertes.fr/hal-01169851

J. Proy, N. Veyrat-charvillon, A. Tisserand, and N. Meloni, Full hardware implementation of short addition chains recoding for ECC scalar multiplication
URL : https://hal.archives-ouvertes.fr/hal-01171095

A. Tisserand, C. ?. Irisa, and . Cairn, Hardware Accelerators for ECC and HECC 34, p.35