R. Cheung, D. Lee, W. Luk, and J. Villasenor, Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, issue.8, 2007.
DOI : 10.1109/TVLSI.2007.900748

F. De-dinechin, M. Istoan, and G. Sergent, Fixed-point trigonometric functions on FPGAs, SIGARCH Computer Architecture News, pp.83-88, 2013.
DOI : 10.1145/2641361.2641375

URL : https://hal.archives-ouvertes.fr/ensl-00802777

F. De-dinechin and M. Istoan, Hardware Implementations of Fixed-Point Atan2, 2015 IEEE 22nd Symposium on Computer Arithmetic, 2015.
DOI : 10.1109/ARITH.2015.23

URL : https://hal.archives-ouvertes.fr/hal-01091138

F. De-dinechin and B. Pasca, Floating-point exponential functions for DSP-enabled FPGAs, 2010 International Conference on Field-Programmable Technology, pp.110-117, 2010.
DOI : 10.1109/FPT.2010.5681764

URL : https://hal.archives-ouvertes.fr/ensl-00506125

F. De-dinechin, P. Echeverría, M. Vallejo, and B. Pasca, Floating-Point Exponentiation Units for Reconfigurable Computing, ACM Transactions on Reconfigurable Technology and Systems, vol.6, issue.1, 2013.
DOI : 10.1145/2457443.2457447

URL : https://hal.archives-ouvertes.fr/ensl-00718637

D. B. Thomas, A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs, 2015 IEEE 22nd Symposium on Computer Arithmetic, 2015.
DOI : 10.1109/ARITH.2015.27

N. Kapre and A. Dehon, Accelerating SPICE Model-Evaluation using FPGAs, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, pp.37-44, 2009.
DOI : 10.1109/FCCM.2009.14

URL : http://authors.library.caltech.edu/18195/1/Kapre2009p8309Proceedings_Of_The_2009_17Th_Ieee_Symposium_On_Field_Programmable_Custom_Computing_Machines.pdf

F. De-dinechin and B. Pasca, High-Performance Computing using FPGAs, ch. Reconfigurable Arithmetic for High Performance Computing, pp.631-664, 2013.

D. Lee, A. Gaffar, O. Mencer, and W. Luk, Optimizing Hardware Function Evaluation, IEEE Transactions on Computers, vol.54, issue.12, pp.1520-1531, 2005.
DOI : 10.1109/TC.2005.201

D. Lee, P. Cheung, W. Luk, and J. Villasenor, Hierarchical segmentation schemes for function evaluation, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798), 2009.
DOI : 10.1109/FPT.2003.1275736

F. De-dinechin, M. Joldes, and B. Pasca, Automatic generation of polynomial-based hardware architectures for function evaluation, ASAP 2010, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, 2010.
DOI : 10.1109/ASAP.2010.5540952

URL : https://hal.archives-ouvertes.fr/ensl-00470506

J. Muller, Elementary Functions, Algorithms and Implementation, 2006.
URL : https://hal.archives-ouvertes.fr/ensl-00000008

F. De-dinechin and B. Pasca, Designing Custom Arithmetic Data Paths with FloPoCo, IEEE Design & Test of Computers, vol.28, issue.4, pp.18-27, 2011.
DOI : 10.1109/MDT.2011.44

URL : https://hal.archives-ouvertes.fr/ensl-00646282

N. Brisebarre and S. Chevillard, Efficient polynomial L-approximations, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.169-176, 2007.
DOI : 10.1109/ARITH.2007.17

URL : https://hal.archives-ouvertes.fr/inria-00119513

S. Chevillard, M. Joldes¸, C. Joldes¸, and . Lauter, Sollya: An Environment for the Development of Numerical Codes, Int. Conf. on Mathematical Software, ser. LNCS, pp.28-31, 2010.
DOI : 10.1007/978-3-642-15582-6_5

URL : https://hal.archives-ouvertes.fr/hal-00761644

S. Chevillard, M. Joldes, and C. Lauter, Certified and Fast Computation of Supremum Norms of Approximation Errors, 2009 19th IEEE Symposium on Computer Arithmetic, pp.169-176, 2009.
DOI : 10.1109/ARITH.2009.18

URL : https://hal.archives-ouvertes.fr/ensl-00334545

J. Detrey and F. De-dinechin, Table-based polynomials for fast hardware function evaluation, " in Application-specific Systems, Architectures and Processors, pp.328-333, 2005.