Towards FHE in Embedded Systems: A Preliminary Co-Design Space Exploration of a HW/SW Very Large Multiplier

Abstract : The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter, we present our first codesign results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.
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Article dans une revue
IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers, 2015, 7 (3), 〈10.1109/LES.2015.2436372〉
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https://hal.inria.fr/hal-01227724
Contributeur : Arnaud Tisserand <>
Soumis le : jeudi 12 novembre 2015 - 09:19:22
Dernière modification le : mercredi 16 mai 2018 - 11:23:27

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Abozaid Ghada, Arnaud Tisserand, El-Mahdy Ahmed, Wada Yasutaka. Towards FHE in Embedded Systems: A Preliminary Co-Design Space Exploration of a HW/SW Very Large Multiplier. IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers, 2015, 7 (3), 〈10.1109/LES.2015.2436372〉. 〈hal-01227724〉

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