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Parallel light speed labeling: An efficient connected component labeling algorithm for multi-core processors

Lionel Lacassagne 1, 2 Laurent Cabaret 2, 3 Daniel Etiemble 3, 2
1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce
LIP6 - Laboratoire d'Informatique de Paris 6
2 LRI - Laboratoire de Recherche en Informatique
3 POSTALE - Performance Optimization by Software Transformation and Algorithms & Librairies Enhancement
LRI - Laboratoire de Recherche en Informatique, Inria Saclay - Ile de France
Abstract : The paper introduces the parallel version of the Light Speed Labeling (LSL) and compares it with the parallel versions of the competitors. A benchmark shows that the parallel Light Speed Labeling is at least ×1.9 faster than all the other algo- rithms for random images. This factor reach ×3.6 for structured random images. More important, we show that thanks to its run-based processing (segments), LSL is intrinsically more efficient than all pixel-based algorithms.
Keywords : parallel algorithm connected component analysis bounding box transitive closure connected component labeling union-find
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Conference papers
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https://hal.inria.fr/hal-01243310
Contributor : Lionel Lacassagne <>
Submitted on : Monday, December 14, 2015 - 7:02:22 PM
Last modification on : Friday, January 8, 2021 - 5:32:08 PM

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CNRS | UPMC | UMR8623 | LIP6 | INRIA | LRI-PARSYS | TDS-MACS | CENTRALESUPELEC | SORBONNE-UNIVERSITE | SU-SCIENCES

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Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble. Parallel light speed labeling: An efficient connected component labeling algorithm for multi-core processors. IEEE International Conference on Image Processing (ICIP), Sep 2015, Quebec, Canada. pp.3486-3489, ⟨10.1109/ICIP.2015.7351452⟩. ⟨hal-01243310⟩

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