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Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture

Sajith Kalathingal 1 Sylvain Collange 1 Bharath Narasimha Swamy 1 André Seznec 1
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Threads of Single-Program Multiple-Data (SPMD) applications often execute the same instructions on different data. We propose the Dynamic Inter-Thread Vectorization Architecture (DITVA) to leverage this implicit Data Level Parallelism in SPMD applications to create dynamic vector instructions at runtime. DITVA extends an SIMD-enabled in-order SMT processor with an inter-thread vectorization execution mode. In this mode, identical instructions of several threads running in lockstep are aggregated into a single SIMD instruction. DITVA leverages existing SIMD units, balances TLP and DLP with a warp/thread hierarchy, and maintains binary compatibility with existing CPU architectures.
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Contributor : Caroline Collange <>
Submitted on : Wednesday, December 16, 2015 - 2:36:12 PM
Last modification on : Thursday, January 7, 2021 - 4:25:04 PM
Long-term archiving on: : Saturday, April 29, 2017 - 4:44:14 PM


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  • HAL Id : hal-01244938, version 1


Sajith Kalathingal, Sylvain Collange, Bharath Narasimha Swamy, André Seznec. Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture. [Research Report] RR-8830, Inria Rennes Bretagne Atlantique. 2015. ⟨hal-01244938⟩



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