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Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture

Sajith Kalathingal 1 Caroline Collange 2 Bharath Narasimha Swamy 1 André Seznec 1
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Threads of Single-Program Multiple-Data (SPMD) applications often execute the same instructions on different data. We propose the Dynamic Inter-Thread Vectorization Architecture (DITVA) to leverage this implicit Data Level Parallelism in SPMD applications to create dynamic vector instructions at runtime. DITVA extends an SIMD-enabled in-order SMT processor with an inter-thread vectorization execution mode. In this mode, identical instructions of several threads running in lockstep are aggregated into a single SIMD instruction. DITVA leverages existing SIMD units, balances TLP and DLP with a warp/thread hierarchy, and maintains binary compatibility with existing CPU architectures.
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https://hal.inria.fr/hal-01244938
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Submitted on : Wednesday, December 16, 2015 - 2:36:12 PM
Last modification on : Monday, April 4, 2022 - 9:28:21 AM
Long-term archiving on: : Saturday, April 29, 2017 - 4:44:14 PM

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  • HAL Id : hal-01244938, version 1

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Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec. Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture. [Research Report] RR-8830, Inria Rennes Bretagne Atlantique. 2015. ⟨hal-01244938⟩

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