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Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation

Jean Perier 1, * Wissem Chouchene 1 Jean-Luc Dekeyser 1
* Corresponding author
1 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages
Inria Lille - Nord Europe, CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189
Abstract : One goal of reconfiguration is to save power and occupied resources. In this paper we compare two different kinds of reconfiguration available on field-programmable gate arrays (FPGA) and we discuss their pros and cons. The first method that we study is circuit merging. This type of reconfiguration methods consists in sharing common resources between different circuits. The second method that we explore is dynamic partial reconfiguration (DPR). It is specific to some FPGA, allowing well defined reconfigurable parts to be modified during run-time. We show that DPR, when available, has good and more predictable result in terms of occupied area. There is still a huge overhead in term of time and power consumption during the reconfiguration phase. Therefore we show that circuit merging remains an interesting solution on FPGA because it is not vendor specific and the reconfiguration time is around a clock cycle. Besides, good merging algorithms exist even-though FPGA physical synthesis flow makes it hard to predict the real performance of the merged circuit during the optimization. We establish our comparison in the context of the HoMade processor.
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Submitted on : Thursday, January 14, 2016 - 6:22:08 PM
Last modification on : Friday, December 11, 2020 - 6:44:06 PM
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  • HAL Id : hal-01245800, version 2

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Jean Perier, Wissem Chouchene, Jean-Luc Dekeyser. Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation. i-manager's Journal on Embedded Systems(JES), i-manager Publications, 2016. ⟨hal-01245800v2⟩

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