D. B. Thomas, L. Howes, and W. Luk, A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '09, pp.63-72, 2009.
DOI : 10.1145/1508128.1508139

F. Hannig, V. Lari, and S. Boppu, Invasive Tightly-Coupled Processor Arrays, ACM Transactions on Embedded Computing Systems, vol.13, issue.4s, pp.1-13329, 2014.
DOI : 10.1145/2584660

F. Conti, C. Pilkington, and A. Marongiu, He-P2012, Proceedings of the 24th edition of the great lakes symposium on VLSI, GLSVLSI '14, pp.114-120, 2014.
DOI : 10.1145/2591513.2591553

M. R. Many-core-kalray, D. M. Haskell, and . Hanna, 9] Next Generation CUDA Compute Architecture: Fermi WhitePaper, http://i.dell.com/sites/doccontent/shared- content/data-sheets/en/Documents/NVIDIA- Fermi-Compute-Architecture-Whitepaperen A VHDL Forth Core for FPGAs, Journal of Microprocessors and Microsystems, vol.29, pp.115-125, 2009.

H. Krichene, M. Baklouti, . Ph, and . Marquet, Broadcast with mask on a massively parallel processing on a chip, 2012 International Conference on High Performance Computing & Simulation (HPCS), pp.275-280, 2012.
DOI : 10.1109/HPCSim.2012.6266924
URL : https://hal.archives-ouvertes.fr/hal-00688418

C. E. Leiserson, Z. S. Abuhamdeh, and D. C. Douglas, The Network Architecture of the Connection Machine CM-5, Journal of Parallel and Distributed Computing, vol.33, issue.2, pp.145-158, 1996.
DOI : 10.1006/jpdc.1996.0033

S. L. Scott, Synchronization and communication in the T3E multiprocessor, Proc. Int. Conf. Architectural Support for Programming Languages and Operating Systems, pp.26-36, 1996.

H. Krichene, M. Baklouti, . Ph, and . Marquet, Master-Slave Control Structure for Massively Parallel System on Chip, 2013 Euromicro Conference on Digital System Design, pp.917-924, 2013.
DOI : 10.1109/DSD.2013.103
URL : https://hal.archives-ouvertes.fr/hal-00906906

M. Leclercq and P. Y. , Aquilanti, X-Net network for MPPSoC, 2006.

M. Baklouti, A rapid design method of a massively parallel System on Chip: from modeling to FPGA implementation, 2010.
URL : https://hal.archives-ouvertes.fr/tel-00527894

P. Chen, K. Dai, and D. Wu, Parallel Algorithms for FIR Computation Mapped to ESCA Architecture, 2010 WASE International Conference on Information Engineering, pp.123-126, 2010.
DOI : 10.1109/ICIE.2010.37

S. M. Kuo and W. S. Gan, Digital Signal Processors Architectures, implementation and application, 2005.

J. R. Nickolls, The design of the MasPar MP-1: a cost effective massively parallel computer, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, pp.25-28, 1990.
DOI : 10.1109/CMPCON.1990.63649

J. Andersson, M. Mohlin, and A. Nilsson, A reconfigurable SIMD architecture on-chip, School of Information Science, 2006.

. Sh, A. Raghav, D. Marongiu, and . Atienza, GPU Acceleration for Simulating Massively Parallel Many-Core Platforms, Journal of Parallel and Distributed Systems, vol.26, pp.1336-1349, 2015.

D. Walsh and P. Dudek, An event-driven massively parallel fine-grained processor array, 2015 IEEE International Symposium on Circuits and Systems (ISCAS)
DOI : 10.1109/ISCAS.2015.7168891