Which Verification for Soft Error Detection?

Abstract : Many methods are available to detect silent errors in high-performance computing (HPC) applications. Each comes with a given cost and recall (fraction of all errors that are actually detected). The main contribution of this paper is to characterize the optimal computational pattern for an application: which detector(s) to use, how many detectors of each type to use, together with the length of the work segment that precedes each of them. We conduct a comprehensive complexity analysis of this optimization problem, showing NP-completeness and designing an FPTAS (Fully Polynomial-Time Approximation Scheme). On the practical side, we provide a greedy algorithm whose performance is shown to be close to the optimal for a realistic set of evaluation scenarios.
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Communication dans un congrès
High Performance Computing 2015, Dec 2015, Bangalore, India. The 22nd annual IEEE International Conference on High Performance Computing (HiPC 2015)
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Leonardo Bautista-Gomez, Anne Benoit, Aurélien Cavelan, Saurabh K. Raina, Yves Robert, et al.. Which Verification for Soft Error Detection?. High Performance Computing 2015, Dec 2015, Bangalore, India. The 22nd annual IEEE International Conference on High Performance Computing (HiPC 2015). 〈hal-01252382〉

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