Time-redundancy transformations for adaptive fault-tolerant circuits

Abstract : We present a novel logic-level circuit transformation technique for the automatic insertion of fault-tolerance properties. The transformations, based on time-redundancy, allow dynamic changes of the level of redundancy without interrupting the computation. The proposed concept of dynamic time redundancy permits adaptive circuits whose fault-tolerance properties can be “on-the-fly” traded-off for throughput. The approach is technologically independent and does not require any specific hardware support. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our method grow with the combinational size of the circuit. Dynamic double and triple time redundant transformations generate circuits 1.7 to 2.9 times smaller than full Triple-Modular Redundancy (TMR). This transformation is a good alternative to TMR for logic-intensive safety-critical circuits where low hardware overhead or only temporary fault-tolerance guarantees are needed.
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Communication dans un congrès
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. 〈10.1109/AHS.2015.7231164〉
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https://hal.inria.fr/hal-01253111
Contributeur : Pascal Fradet <>
Soumis le : vendredi 8 janvier 2016 - 16:25:50
Dernière modification le : samedi 9 janvier 2016 - 01:07:17

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Dmitry Burlyaev, Pascal Fradet, Alain Girault. Time-redundancy transformations for adaptive fault-tolerant circuits. 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. 〈10.1109/AHS.2015.7231164〉. 〈hal-01253111〉

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