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Design and Implementation of an Espionage Network for Cache-based Side Channel Attacks on AES

Abstract : We design and implement the espionage infrastructure to launch a cache-based side channel attack on AES. This includes a spy controller and a ring of spy threads with associated analytic capabilities – all hosted on a single server. By causing the victim process (which repeatedly performs AES encryptions) to be interrupted, the spy threads capture the victim’s footprints in the cache memory where the lookup tables reside. Preliminary results indicate that our setup can deduce the encryption key in fewer than 30 encryptions and with far fewer victim interruptions compared to previous work. Moreover, this approach can be easily adapted to work on diverse hardware/OS platforms and on different versions of OpenSSL.
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https://hal.inria.fr/hal-01253262
Contributor : Ravi Prakash Giri <>
Submitted on : Monday, January 11, 2016 - 8:54:50 PM
Last modification on : Friday, January 11, 2019 - 3:46:22 PM

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Bholanath Roy, Ravi Prakash Giri, Ashokkumar C, Bernard Menezes. Design and Implementation of an Espionage Network for Cache-based Side Channel Attacks on AES . International Conference on Security and Cryptography (SECRYPT), May 2015, Colmar, Alsace, France. pp.441-447, ⟨10.5220/0005576804410447⟩. ⟨hal-01253262⟩

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