A. Jaleel, K. B. Theobald, S. C. Steely, J. , and J. Emer, High performance cache replacement using rereference interval prediction (RRIP), ISCA, 2010.
DOI : 10.1145/1815961.1815971

V. Seshadri, O. Mutlu, M. A. Kozuch, and T. C. Mowry, The evicted-address filter, Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12
DOI : 10.1145/2370816.2370868

A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely et al., Adaptive insertion policies for managing shared caches, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, 2008.
DOI : 10.1145/1454115.1454145

K. Moinuddin, A. Qureshi, Y. N. Jaleel, S. C. Patt, J. Steely et al., Adaptive insertion policies for high performance caching, ISCA, 2007.

C. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. C. Steely et al., SHiP, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11
DOI : 10.1145/2155620.2155671

URL : https://hal.archives-ouvertes.fr/hal-01314834

K. Moinuddin, Y. N. Qureshi, and . Patt, Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, 2006.

K. J. Nesbit, J. Laudon, and J. E. Smith, Virtual private caches, ISCA, 2007.
DOI : 10.1145/1273440.1250671

Y. Xie and G. H. Loh, PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches, ISCA, 2009.

R. Iyer, CQoS, Proceedings of the 18th annual international conference on Supercomputing , ICS '04, 2004.
DOI : 10.1145/1006209.1006246

A. Gupta, J. Sampson, and M. B. Taylor, TimeCube: A manycore embedded processor with interference-agnostic progress tracking, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013.
DOI : 10.1109/SAMOS.2013.6621127

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.307.1885

M. Chaudhuri, J. Gaur, N. Bashyam, S. Subramoney, and J. Nuzman, Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches, Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12
DOI : 10.1145/2370816.2370860

H. Gao and C. Wilkerson, A Dueling Segmented LRU Replacement Algorithm with Adaptive Bypassing, Joel Emer. JWAC 2010 -1st JILP Worshop on Computer Architecture Competitions: cache replacement Championship
URL : https://hal.archives-ouvertes.fr/inria-00492965

D. Jamison, D. M. Collins, and . Tullsen, Hardware identification of cache conflict misses, MICRO, 1999.

T. L. Johnson, D. A. Connors, M. C. Merten, and W. W. Hwu, Run-time cache bypassing, IEEE TC, 1999.
DOI : 10.1109/12.817393

G. Kurian, O. Khan, and S. Devadas, The locality-aware adaptive cache coherence protocol, ISCA 2013

J. Gaur, M. Chaudhuri, and S. Subramoney, Bypass and insertion algorithms for exclusive last-level caches, ISCA, 2011.
DOI : 10.1145/2024723.2000075

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.220.7987

A. Gonzlez, C. Aliagas, and M. Valero, A data cache with multiple caching strategies tuned to different types of locality, ICS, 1995.

S. Mcfarling, Cache replacement with dynamic exclusion, ISCA, 1992.

R. A. Velasquez, P. Michaud, A. Seznec, and . Badco, Behavioral Application-Dependent Superscalar Core model, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00707346

O. Mutlu and T. Moscibroda, Parallelism-Aware Batch Scheduling, ISCA, 2008.
DOI : 10.1145/1394608.1382128

W. Lin and S. K. Reinhardt, Predicting Last- Touch References under Optimal Replacement, 2002.

H. Liu, M. Ferdman, J. Huh, and D. Burger, Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency, 2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008.
DOI : 10.1109/MICRO.2008.4771793

A. Lai, C. Fide, and B. Falsafi, Dead-block prediction & dead-block correlating prefetchers, ISCA, 2001.

S. Tripti, B. Warrier, M. Anupama, and . Mutyam, An application-aware cache replacement policy for last-level caches, ARCS 2013

S. M. Khan, Y. Tian, and D. A. Jimenez, Sampling Dead Block Prediction for Last-Level Caches, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010.
DOI : 10.1109/MICRO.2010.24

URL : http://cava.cs.utsa.edu/pdfs/micro2010_sampler_dist.pdf

R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger, Evaluation techniques for storage hierarchies, IBM Systems Journal, vol.9, issue.2, 1970.
DOI : 10.1147/sj.92.0078

P. Michaud, Demystifying multicore throughput metrics, IEEE Computer Architecture Letters, vol.12, issue.2, 2013.
DOI : 10.1109/L-CA.2012.25

URL : https://hal.archives-ouvertes.fr/hal-00737044

Z. Zhang, Z. Zhu, and X. Zhang, A permutation-based page interleaving scheme to reduce rowbuffer conflicts and exploit data locality, 2000.

R. Manikantan, K. Rajan, and R. Govindarajan, Probabilistic shared cache management (PriSM), 2012.
DOI : 10.1109/isca.2012.6237037

D. Sanchez and C. Kozyrakis, Vantage: scalable and efficient fine-grain cache partitioning, ISCA, 2011.
DOI : 10.1109/mm.2012.19

N. Beckmann and D. Sanchez, Jigsaw: scalable software-defined caches, PACT 2013

R. Manikantan, K. Rajan, and R. Govindarajan, NUcache: An efficient multicore cache organization based on Next-Use distance, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011.
DOI : 10.1109/HPCA.2011.5749733

G. Keramidas, P. Petoumenos, and S. Kaxiras, Cache replacement based on reuse-distance prediction, 2007 25th International Conference on Computer Design, 2007.
DOI : 10.1109/ICCD.2007.4601909

M. Kharbutli and Y. Solihin, Counter-Based Cache Replacement and Bypassing Algorithms, IEEE Transactions on Computers, vol.57, issue.4, 2008.
DOI : 10.1109/TC.2007.70816

D. Eklov, D. Black-schaffer, and E. Hagersten, Fast modeling of shared caches in multicore systems, Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC '11, 2011.
DOI : 10.1145/1944862.1944885

. Pai, Accelerating multicore reuse distance analysis with sampling and parallelizationbenefit-of- cache-monitoring, 2010.

K. Luo, J. Gummaraju, and M. Franklin, Balancing thoughput and fairness in SMT processors, 2001.