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An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis

Abstract : A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems if improperly implemented. Formal verification techniques are needed to check the correctness of the design. This paper describes the discovery of a potential livelock problem through formal analysis on an extension of the link-fault tolerant NoC architecture introduced by Wu et al. In the process of eliminating this problem, an improved routing architecture is derived. The improvement simplifies the routing architecture, enabling successful verification using the CADP verification toolbox. The routing algorithm is proven to have several desirable properties including deadlock and livelock freedom, and tolerance to a single-link-fault.
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https://hal.inria.fr/hal-01261234
Contributor : Wendelin Serwe <>
Submitted on : Monday, January 25, 2016 - 7:29:07 AM
Last modification on : Tuesday, February 9, 2021 - 3:10:03 PM
Long-term archiving on: : Tuesday, April 26, 2016 - 10:22:36 AM

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Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, et al.. An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Science of Computer Programming, Elsevier, 2016, ⟨10.1016/j.scico.2016.01.002⟩. ⟨hal-01261234⟩

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