??thereal Network on Chip:Concepts, Architectures, and Implementations, IEEE Design and Test of Computers, vol.22, issue.5, pp.414-421, 2005. ,
DOI : 10.1109/MDT.2005.99
HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, 2004. ,
DOI : 10.1016/j.vlsi.2004.03.003
QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture, vol.50, issue.2-3, 2004. ,
DOI : 10.1016/j.sysarc.2003.07.004
A fault-tolerant routing algorithm for a network-on-chip using a link fault model, in: Virtual Worldwide Forum for PhD Researchers in Electronic Design Automation, 2011. ,
CADP 2011: a toolbox for the construction and analysis of distributed processes, International Journal on Software Tools for Technology Transfer, vol.1, issue.1/2, pp.89-107, 2013. ,
DOI : 10.1007/s10009-012-0244-z
URL : https://hal.archives-ouvertes.fr/hal-00715056
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip, Formal Methods for Industrial Critical Systems, pp.48-62, 2014. ,
DOI : 10.1007/978-3-319-10702-8_4
URL : https://hal.archives-ouvertes.fr/hal-01064829
Fault-tolerant wormhole routing in meshes, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing, pp.240-249, 1993. ,
DOI : 10.1109/FTCS.1993.627327
Improving Dependability and Performance of Fully Asynchronous On-chip Networks, 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, pp.65-76, 2011. ,
DOI : 10.1109/ASYNC.2011.15
Compositional verification of asynchronous concurrent systems using CADP, Acta Informatica, vol.56, issue.1/2, pp.337-392, 2015. ,
DOI : 10.1007/s00236-015-0226-1
URL : https://hal.archives-ouvertes.fr/hal-01247507
SVL: A Scripting Language for Compositional Verification, Proceedings of the 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems FORTE'2001, pp.377-392, 2001. ,
DOI : 10.1007/0-306-47003-9_24
URL : https://hal.archives-ouvertes.fr/inria-00072396
Smart Reduction, Proceedings of the 14th International Conference on Fundamental Approaches to Software Engineering FASE 2011, pp.111-126, 2011. ,
DOI : 10.1007/978-3-642-19811-3_9
URL : https://hal.archives-ouvertes.fr/inria-00572535
Property-Dependent Reductions for the Modal Mu-Calculus, Proceedings of the 18th International SPIN Workshop on Model Checking Software SPIN'2011, pp.2-19, 2011. ,
DOI : 10.1007/978-3-642-22306-8_2
URL : https://hal.archives-ouvertes.fr/inria-00609585
Branching bisimilarity with explicit divergence, Fundamenta Informaticae, vol.93, issue.4, pp.371-392, 2009. ,
Branching-Time and Abstraction in Bisimulation Semantics (extended abstract, CS R8911, Centrum Wiskunde & Informatica (CWI) Proceedings of the 11th IFIP World Computer Congress, p.1989, 1989. ,
A Model Checking Language for Concurrent Value-Passing Systems, Proceedings of the 15th International Symposium on Formal Methods FM'08, pp.148-164, 2008. ,
DOI : 10.1007/978-3-540-68237-0_12
URL : https://hal.archives-ouvertes.fr/inria-00315312
A protocol for deadlock-free dynamic reconfiguration in high-speed local area networks, IEEE Transactions on Parallel and Distributed Systems, vol.12, issue.2, pp.115-132, 2001. ,
DOI : 10.1109/71.910868
A highly resilient routing algorithm for fault-tolerant NoCs, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.21-26, 2009. ,
DOI : 10.1109/DATE.2009.5090627
A theory of fault-tolerant routing in wormhole networks, IEEE Transactions on Parallel and Distributed Systems, vol.8, issue.8, pp.790-802, 1997. ,
DOI : 10.1109/71.605766
A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes, Network and Parallel Computing, IFIP International Conference, pp.341-356, 2004. ,
DOI : 10.1137/0211027
A fault-tolerant and deadlock-free routing protocol in 2d meshes based on odd-even turn model, IEEE Transactions on Computers, vol.52, issue.9, pp.1154-1169, 2003. ,
Fault-tolerant wormhole routing algorithms for mesh networks, IEEE Transactions on Computers, vol.44, issue.7, pp.848-864, 1995. ,
DOI : 10.1109/12.392844
Fault-tolerant routing algorithm for meshes without using virtual channels, J. Inf. Sci. Eng, vol.14, issue.4, pp.765-783, 1998. ,
Adaptive fault-tolerant wormhole routing in 2d meshes, Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), pp.56-66, 2001. ,
Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture, vol.50, issue.2-3, 2004. ,
DOI : 10.1016/j.sysarc.2003.07.005
Adaptive routing scheme for NoC communication architecture, ICACT 2005. The 7th International Conference on, pp.1180-1184, 2005. ,
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp.527-534, 2007. ,
DOI : 10.1109/DSD.2007.4341518
Validation of Asynchronous Circuit Specifications Using IF/CADP, International Federation for Information Processing, pp.85-100, 2006. ,
DOI : 10.1007/0-387-33403-3_6
URL : https://hal.archives-ouvertes.fr/hal-00107431
On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP, Sci, Comput. Program, vol.74, issue.3, 2009. ,
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), pp.73-82, 2007. ,
DOI : 10.1109/ASYNC.2007.18
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005. ,
DOI : 10.1109/ASYNC.2005.10
The odd-even turn model for adaptive routing, IEEE Transactions on Parallel and Distributed Systems, vol.11, issue.7, pp.729-738, 2000. ,
DOI : 10.1109/71.877831
Formal modeling and verification for Network-on-chip, The 2010 International Conference on Green Circuits and Systems, pp.299-304, 2010. ,
DOI : 10.1109/ICGCS.2010.5543050
Application of Formal Methods for System-Level Verification of Network on Chip, 2011 IEEE Computer Society Annual Symposium on VLSI, pp.4-6, 2011. ,
DOI : 10.1109/ISVLSI.2011.57
Modeling and formal verification of a passive optical network on chip behavior, Electronic Communications of the EASST 21 ,
On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks, IEEE Transactions on Parallel and Distributed Systems, vol.22, issue.12, pp.2022-2032, 2011. ,
DOI : 10.1109/TPDS.2011.60
A Decision Procedure for Deadlock-Free Routing in Wormhole Networks, IEEE Transactions on Parallel and Distributed Systems, vol.25, issue.8 ,
DOI : 10.1109/TPDS.2013.121
Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching, Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, NOCS '11, pp.25-32, 2011. ,
DOI : 10.1145/1999946.1999951
Fully reliable dynamic routing logic for a fault-tolerant NoC architecture, Journal of Integrated Circuits and Systems, vol.8, issue.1, pp.43-53, 2013. ,
A Formal Approach to the Verification of Networks on Chip, EURASIP Journal on Embedded Systems, vol.2009, issue.1, pp.1-2, 2009. ,
DOI : 10.1016/j.vlsi.2004.03.003
URL : https://hal.archives-ouvertes.fr/hal-00419368
Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.221-224, 2010. ,
DOI : 10.1109/DDECS.2010.5491781
URL : https://hal.archives-ouvertes.fr/hal-00517659
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures, ACM Transactions on Design Automation of Electronic Systems, vol.17, issue.1, pp.1-1, 2012. ,
DOI : 10.1145/2071356.2071357