. Embedded and . Com, 2009 embedded market studyblogs/embedded-market-surveys, 2009.

T. Grandpierre and Y. Sorel, From algorithm and architecture specification to automatic generation of distributed real-time executives, Proceedings MEMOCODE, 2003.

S. S. Craciunas and R. S. Oliver, SMT-based Task- and Network-level Static Schedule Generation for Time-Triggered Networked Systems, Proceedings of the 22nd International Conference on Real-Time Networks and Systems, RTNS '14, 2014.
DOI : 10.1145/2659787.2659812

T. Carle, D. Potop-butucaru, Y. Sorel, and D. Lesens, From dataflow specification to multiprocessor partitioned time-triggered real-time implementation, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00742908

T. Carle and D. Potop-butucaru, Predicate-aware, makespanpreserving software pipelining of scheduling tables, ACM Transactions on Architecture and Code Optimization, vol.11, issue.1, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01095123

A. Cohen, V. Perrelle, D. Potop-butucaru, E. Soubiran, and Z. Zhan, Mixed-criticality in railway systems: A case study on signalling application, WMCIS Proceedings of the Workshop on Mixed Criticality for Industrial Systems, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01095111

D. Monchaux, P. Gast, and J. Sangare, Avionic-x: A demonstrator for the next generation launcher avionics, Proceedings ERTS², 2012.

T. Carle, M. Djemal, D. Potop-butucaru, R. D. Simone, and Z. Zhang, Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays, 2014 14th International Conference on Application of Concurrency to System Design, 2014.
DOI : 10.1109/ACSD.2014.19
URL : https://hal.archives-ouvertes.fr/hal-01095130

T. Carle, M. Djemal, D. Genius, F. Pêcheux, D. Potop-butucaru et al., Reconciling performance and predictability on a many-core through off-line mapping, 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014.
DOI : 10.1109/ReCoSoC.2014.6861367
URL : https://hal.archives-ouvertes.fr/hal-01095116

H. Kopetz and G. Bauer, The time-triggered architecture, Proceedings of the IEEE, vol.91, issue.1, pp.138-144, 2003.

. Tte-plan, The TTEthernet Scheduler, 2013.