K. Altisen, A. Clodic, F. Maraninchi, and E. Rutten, Using controllersynthesis techniques to build property-enforcing layers, Proc. 12th European Conference on Programming, ESOP'03, pp.174-188, 2003.
DOI : 10.1007/3-540-36575-3_13

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.102.2186

X. An, High Level Design and Control of Adaptive MPSoCs, 2013.

X. An, E. Rutten, J. Diguet, N. Le-griguer, and A. Gamatié, Autonomic management of dynamically partially reconfigurable fpga architectures using discrete control, Proc. 10th Int. Conf. Autonomic Computing (ICAC'13), pp.59-63, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00852849

X. An, E. Rutten, J. Diguet, N. Le-griguer, and A. Gamatié, Discrete Control for Reconfigurable FPGA-based Embedded Systems*, Proc. 4th IFAC Workshop on DCDS, pp.151-156, 2013.
DOI : 10.3182/20130904-3-UK-4041.00017

URL : https://hal.archives-ouvertes.fr/hal-00862489

J. Aylward, C. H. Crawford, K. Inoue, S. Lekuch, K. Müller et al., Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures, 2011 International Conference on Reconfigurable Computing and FPGAs, pp.351-356, 2011.
DOI : 10.1109/ReConFig.2011.78

R. Bévan, J. Lallican, W. Allègre, and P. Berruet, The simsed framework for modelling and simulation of transitic systems under uncertain environment, 9th Int. Industrial Simulation Conf, pp.11-17, 2011.

O. Dahmoune, R. De, and B. Johnston, Applying model-checking to postsilicon-verification: Bridging the specification-realisation gap, Proc. Conf. on ReConFig, pp.73-78, 2010.

G. Delaval, H. Marchand, and E. Rutten, Contracts for modular discrete controller synthesis, Conf. on Languages, Compilers, and Tools for Embedded Systems, pp.57-66, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00436560

E. Dumitrescu, A. Girault, H. Marchand, and E. Rutten, Multicriteria optimal discrete controller synthesis for fault-tolerant tasks, Workshop on Discrete Event Systems, pp.366-373, 2010.

Y. Eustache and J. Diguet, Specification and OS-based implementation of self-adaptive, hardware/software embedded systems, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, CODES/ISSS '08, pp.67-72, 2008.
DOI : 10.1145/1450135.1450151

URL : https://hal.archives-ouvertes.fr/hal-00369071

A. Gamatié, H. Yu, G. Delaval, and E. Rutten, A Case Study on Controller Synthesis for Data-Intensive Embedded Systems, 2009 International Conference on Embedded Software and Systems, pp.75-82, 2009.
DOI : 10.1109/ICESS.2009.12

F. Ghaffari, M. Auguin, M. Abid, and M. B. Jemaa, Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures, Transactions on High-Performance Embedded Architectures and Compilers I, pp.179-193, 2007.
DOI : 10.1023/A:1008857008151

D. Gohringer, M. Hubner, V. Schatz, and J. Becker, Runtime adaptive multiprocessor system-on-chip: RAMPSoC, Symp. on Parallel & Distributed Processing, pp.1-7, 2008.

L. Gong and O. Diessel, Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, pp.9-16, 2011.
DOI : 10.1109/FCCM.2011.18

S. Guillet, F. De-lamotte, N. Le-griguer, E. Rutten, G. Gogniat et al., Designing formal reconfiguration control using UML/MARTE, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp.1-8, 2012.
DOI : 10.1109/ReCoSoC.2012.6322870

URL : https://hal.archives-ouvertes.fr/hal-00747716

S. Guillet, F. De-lamotte, N. Le-griguer, E. Rutten, G. Gogniat et al., Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling, ACM Transactions on Reconfigurable Technology and Systems, vol.7, issue.3, pp.1-2717, 2014.
DOI : 10.1145/2629628

URL : https://hal.archives-ouvertes.fr/hal-00972636

H. Hinkelmann, P. Zipf, and M. Glesner, Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes, 2009 International Conference on Field Programmable Logic and Applications, pp.359-366, 2009.
DOI : 10.1109/FPL.2009.5272268

S. Jovanovi?, C. Tanougast, and S. Weber, A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems, Reconfigurable Computing: Architectures, Tools and Applications, pp.160-171, 2008.
DOI : 10.1007/978-3-540-78610-8_17

C. Lu, J. A. Stankovic, S. H. Son, and G. Tao, Feedback control realtime scheduling: Framework, modeling and algorithms. Real-Time Systems Journal, pp.85-126, 2002.

F. Madlener, J. Weingart, and S. A. Huss, Verification of dynamically reconfigurable embedded systems by model transformation rules, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, pp.33-40, 2010.
DOI : 10.1145/1878961.1878969

M. Maggio, H. Hoffmann, A. V. Papadopoulos, J. Panerati, M. D. Santambrogio et al., Comparison of Decision-Making Strategies for Self-Optimization in Autonomic Computing Systems, ACM Transactions on Autonomous and Adaptive Systems, vol.7, issue.4, pp.1-3632, 2012.
DOI : 10.1145/2382570.2382572

M. Majer, J. Teich, A. Ahmadinia, and C. Bobda, The erlangen slot machine: A dynamically reconfigurable fpga-based computer. The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, pp.15-31, 2007.

H. Marchand and M. Samaan, Incremental design of a power transformer station controller using a controller synthesis methodology, IEEE Transactions on Software Engineering, vol.26, issue.8, pp.729-741, 2000.
DOI : 10.1109/32.879811

URL : https://hal.archives-ouvertes.fr/hal-00546156

G. Martin, B. Bailey, and A. Piziali, ESL design and verification: a prescription for electronic system level methodology, 2010.

C. Maxfield, The design warrior's guide to FPGAs: devices, tools and flows, 2004.

J. Noguera and R. M. Badia, Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling, ACM Transactions on Embedded Computing Systems, vol.3, issue.2, pp.385-406, 2004.
DOI : 10.1145/993396.993404

V. Nollet, P. Avasare, H. Eeckhaut, D. Verkest, and H. Corporaal, Run-Time Management of a MPSoC Containing FPGA Fabric Tiles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, issue.1, pp.24-33, 2008.
DOI : 10.1109/TVLSI.2007.912097

K. Paulsson, M. Hubner, and J. Becker, Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), pp.288-291, 2006.
DOI : 10.1109/AHS.2006.67

I. R. Quadri, H. Yu, A. Gamatié, E. Rutten, S. Meftali et al., Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation, International Journal of Embedded Systems, vol.4, issue.3/4, pp.204-224, 2010.
DOI : 10.1504/IJES.2010.039025

URL : https://hal.archives-ouvertes.fr/inria-00525015

P. J. Ramadge and W. M. Wonham, The control of discrete event systems, Proc. of the IEEE, pp.81-98, 1989.
DOI : 10.1109/5.21072

S. Singh and C. J. Lillieroth, Formal verification of reconfigurable cores, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375), pp.25-32, 1999.
DOI : 10.1109/FPGA.1999.803664

F. Sironi, M. Triverio, H. Hoffmann, M. Maggio, and M. D. Santambrogio, Self-Aware Adaptation in FPGA-based Systems, 2010 International Conference on Field Programmable Logic and Applications, pp.187-192, 2010.
DOI : 10.1109/FPL.2010.43

D. Suzuki, . Natsui, . Mochizuki, H. Miura, K. Honjo et al., Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications, IEICE Electronics Express, vol.10, issue.23, p.1020130772, 2013.
DOI : 10.1587/elex.10.20130772

K. S. Vallerio and N. K. Jha, Task graph extraction for embedded system synthesis, 16th International Conference on VLSI Design, 2003. Proceedings., pp.480-486, 2003.
DOI : 10.1109/ICVD.2003.1183180

J. Vidal, F. De-lamotte, G. Gogniat, P. Soulard, and J. Diguet, A codesign approach for embedded system modeling and code generation with uml and marte, DATE, pp.226-231, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00369036

L. Ye, J. Diguet, and G. Gogniat, Rapid Application Development on Multi-processor Reconfigurable Systems, 2010 International Conference on Field Programmable Logic and Applications, pp.285-290, 2010.
DOI : 10.1109/FPL.2010.65

URL : https://hal.archives-ouvertes.fr/hal-00488527