Service interruption on Monday 11 July from 12:30 to 13:00: all the sites of the CCSD (HAL, Epiciences, SciencesConf, AureHAL) will be inaccessible (network hardware connection).
Skip to Main content Skip to Navigation
Conference papers

Sequential PDEVS Architecture

Damián Vicino 1 Daniella Niyonkuru 2 Gabriel Wainer 2 Olivier Dalle 1 
1 SCALE - Safe Composition of Autonomous applications with Large-SCALE Execution environment
CRISAM - Inria Sophia Antipolis - Méditerranée , Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : Parallel Discrete Event System Specification (PDEVS) is a well-known formalism used to model and simulate Discrete Event Systems. This formalism uses an abstract simulator that defines a set of abstract algorithms that are parallel by nature. To implement simulators using these abstract algorithms , several architectures were proposed. Most of these architectures follow distributed approaches that may not be appropriate for single core processors or microcontrollers. In order to reuse efficiently PDEVS models in this type of systems, we define a new architecture that provides a single threaded execution by passing messages in a call/return fashion to simplify the execution time analysis.
Document type :
Conference papers
Complete list of metadata

Cited literature [19 references]  Display  Hide  Download
Contributor : Olivier Dalle Connect in order to contact the contributor
Submitted on : Friday, February 19, 2016 - 3:56:06 PM
Last modification on : Saturday, June 25, 2022 - 11:18:39 PM
Long-term archiving on: : Friday, May 20, 2016 - 10:28:15 AM


Files produced by the author(s)




  • HAL Id : hal-01274279, version 1



Damián Vicino, Daniella Niyonkuru, Gabriel Wainer, Olivier Dalle. Sequential PDEVS Architecture. Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium , 2015, Alexandria, Virginia, United States. ⟨hal-01274279⟩



Record views


Files downloads