Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms

Abstract : In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
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Communication dans un congrès
Luis M. Camarinha-Matos; Nuno S. Barrento; Ricardo Mendonça. 5th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2014, Costa de Caparica, Portugal. Springer, IFIP Advances in Information and Communication Technology, AICT-423, pp.543-550, 2014, Technological Innovation for Collective Awareness Systems. 〈10.1007/978-3-642-54734-8_60〉
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Vladimir Verstov, Vadim Shakhnov, Lyudmila Zinchenko. Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms. Luis M. Camarinha-Matos; Nuno S. Barrento; Ricardo Mendonça. 5th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2014, Costa de Caparica, Portugal. Springer, IFIP Advances in Information and Communication Technology, AICT-423, pp.543-550, 2014, Technological Innovation for Collective Awareness Systems. 〈10.1007/978-3-642-54734-8_60〉. 〈hal-01274821〉

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