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Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms
Abstract : In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
Cited literature [9 references]
https://hal.inria.fr/hal-01274821
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Submitted on : Tuesday, February 16, 2016 - 11:34:27 AM
Last modification on : Thursday, May 12, 2016 - 10:38:58 AM
Long-term archiving on: : Tuesday, May 17, 2016 - 5:22:53 PM
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Tuesday, February 16, 2016 - 11:34:27 AM
Last modification on : Thursday, May 12, 2016 - 10:38:58 AM
Long-term archiving on: : Tuesday, May 17, 2016 - 5:22:53 PM
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