Abstract : In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
https://hal.inria.fr/hal-01274821 Contributor : Hal IfipConnect in order to contact the contributor Submitted on : Tuesday, February 16, 2016 - 11:34:27 AM Last modification on : Thursday, May 12, 2016 - 10:38:58 AM Long-term archiving on: : Tuesday, May 17, 2016 - 5:22:53 PM
Vladimir Verstov, Vadim Shakhnov, Lyudmila Zinchenko. Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms. 5th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2014, Costa de Caparica, Portugal. pp.543-550, ⟨10.1007/978-3-642-54734-8_60⟩. ⟨hal-01274821⟩