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A 0.5 V Ultra-low Power Quadrature Ring Oscillator
Abstract : In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topology capable to generate quadrature signals. Simulations results in a 130 nm CMOS technology shows that a very simple VCO in the GHz range can be obtained, by changing the bulk voltage of transistors (NMOS or PMOS). The circuit operates with less than 50 μW achieving a FoM of about -115 dBc/Hz at 10 MHz offset.
Cited literature [5 references]
https://hal.inria.fr/hal-01274825
Contributor : Hal Ifip <>
Submitted on : Tuesday, February 16, 2016 - 11:35:56 AM
Last modification on : Thursday, June 4, 2020 - 6:26:03 PM
Long-term archiving on: : Tuesday, May 17, 2016 - 5:23:56 PM
Contributor : Hal Ifip <>
Submitted on : Tuesday, February 16, 2016 - 11:35:56 AM
Last modification on : Thursday, June 4, 2020 - 6:26:03 PM
Long-term archiving on: : Tuesday, May 17, 2016 - 5:23:56 PM
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