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Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects

Abstract : Optical technology promises to solve the bottleneck communication in Multiprocessor Systems-on-Chip (MPSoCs) by integrating high speed interconnections. From the system point of view, one of the most critical problems in optical communication is channel bandwidth, strongly influencing the system performance and cost. Channel bandwidth establishes the number of waveguides and wavelengths to serve each communication request. Dynamic approaches allow to define the channel bandwidth at the runtime, which leadsflexible systems but may turn their performance unpredictable. Design-time approaches appear as an attractive alternative to define the channel bandwidth for systems that require performance guarantees and simple solutions. A method for exploring the channel bandwidth design space is thus mandatory in order to identify the best communication channel size. In this work we explore the trade-off among channel bandwidth alternatives, performance, area and power. We show that the channel size has a strong impact on the system performance and cost. We employ synthetic and real application traffic, which has been executed on Gem5. As a result we show that different channel bandwidth can improve the execution time of an application up to 75% while including low area and power penalties. In this talk we will also explore how error correction codes can help reducing power consumption of the optical components.
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Contributor : Daniel Chillet Connect in order to contact the contributor
Submitted on : Thursday, March 24, 2016 - 6:27:43 PM
Last modification on : Wednesday, November 3, 2021 - 6:04:13 AM


2016-Optics - V9.pptx.pdf
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  • HAL Id : hal-01293506, version 1


Olivier Sentieys, Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cedric Killian, et al.. Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects. 2th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), co-located with IEEE/ACM Design Automation and Test in Europe (DATE’16), Mar 2016, Dresden, Germany. ⟨hal-01293506⟩



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