Balancing thoughput and fairness in SMT processors, IEEE International Symposium on Performance Analysis of Systems and Software, pp.164-171, 2001. ,
Coordinated control of multiple prefetchers in multi-core systems, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, pp.316-326, 2009. ,
DOI : 10.1145/1669112.1669154
Inside intel core microarchitecture and smart memory access, intel technical white paper, 2006. ,
AC/DC: an adaptive data cache prefetcher, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004., pp.135-145, 2004. ,
DOI : 10.1109/PACT.2004.1342548
Access map pattern matching for high performance data cache prefetch, J. Instruction-Level Parallelism, vol.13, 2011. ,
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers, 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp.63-74, 2007. ,
DOI : 10.1109/HPCA.2007.346185
Prefetchaware shared resource management for multi-core systems, Proceedings of the 38th Annual International Symposium on Computer Architecture, pp.141-152, 2011. ,
Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems, Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, ASPLOS XV, pp.335-346, 2010. ,
MISE: Providing performance predictability and improving fairness in shared main memory systems, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), pp.639-650, 2013. ,
DOI : 10.1109/HPCA.2013.6522356
APC: A Novel Memory Metric and Measurement Methodology for Modern Memory Systems, IEEE Transactions on Computers, vol.63, issue.7, pp.1626-1639, 2014. ,
DOI : 10.1109/TC.2013.38
PACMan, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, pp.442-453, 2011. ,
DOI : 10.1145/2155620.2155672
Prefetch-Aware DRAM Controllers, 2008 41st IEEE/ACM International Symposium on Microarchitecture, pp.200-209, 2008. ,
DOI : 10.1109/MICRO.2008.4771791
The gem5 simulator, SIGARCH Comput. Archit. News, 2011. ,
DOI : 10.1145/2024716.2024718
Probabilistic shared cache management (PriSM), Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA '12, pp.428-439, 2012. ,
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, pp.47-623, 2014. ,
DOI : 10.1109/MICRO.2014.29
Symbiotic job scheduling for a simultaneous multithreaded processor, Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, pp.234-244, 2000. ,
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), pp.146-160, 2007. ,
DOI : 10.1109/MICRO.2007.21
SHiP, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, pp.44-430, 2011. ,
DOI : 10.1145/2155620.2155671
URL : https://hal.archives-ouvertes.fr/hal-01314834
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp.65-76, 2010. ,
DOI : 10.1109/MICRO.2010.51
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost, 2014 IEEE 32nd International Conference on Computer Design (ICCD), pp.8-15, 2014. ,
DOI : 10.1109/ICCD.2014.6974655
Modern Differential Geometry of Curves and Surfaces with Mathematica, 1996. ,
TCPT - Thread criticality-driven prefetcher throttling, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, pp.399-400, 2013. ,
DOI : 10.1109/PACT.2013.6618835
ABS, ACM Transactions on Architecture and Code Optimization, vol.8, issue.4, pp.1-1920, 2012. ,
DOI : 10.1145/2086696.2086698
Making data prefetch smarter, Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12, pp.137-146, 2012. ,
DOI : 10.1145/2370816.2370837
Increasing multicore system efficiency through intelligent bandwidth shifting, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp.39-50, 2015. ,
DOI : 10.1109/HPCA.2015.7056020
A hardware-based cache pollution filtering mechanism for aggressive prefetches, 2003 International Conference on Parallel Processing, 2003. Proceedings., pp.286-293, 2003. ,
DOI : 10.1109/ICPP.2003.1240591
Characterization and dynamic mitigation of intra-application cache interference, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE, pp.2-11, 2011. ,
DOI : 10.1109/ISPASS.2011.5762710
Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors, Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, SIGMETRICS '11, pp.37-48, 2011. ,
DOI : 10.1145/1993744.1993749
Best-offset hardware prefetching, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016. ,
DOI : 10.1109/HPCA.2016.7446087
URL : https://hal.archives-ouvertes.fr/hal-01254863
The application slowdown model, Proceedings of the 48th International Symposium on Microarchitecture, MICRO-48, pp.62-75, 2015. ,
DOI : 10.1145/2830772.2830803