Average Bit-Complexity of Euclidean Algorithms, Proc. 27th International Colloquium Automata, Languages and Programming (ICALP), pp.373-387, 2000. ,
DOI : 10.1007/3-540-45022-X_32
An RNS Montgomery modular multiplication algorithm, IEEE Transactions on Computers, vol.47, issue.7, pp.766-776, 1998. ,
DOI : 10.1109/12.709376
RNS Arithmetic Approach in Lattice-Based Cryptography: Accelerating the "Rounding-off" Core Procedure, 2015 IEEE 22nd Symposium on Computer Arithmetic, pp.113-120, 2015. ,
DOI : 10.1109/ARITH.2015.30
a full RNS implementation of RSA, IEEE Transactions on Computers, vol.53, issue.6, pp.769-774, 2004. ,
DOI : 10.1109/TC.2004.2
URL : https://hal.archives-ouvertes.fr/lirmm-00108553
Leak Resistant Arithmetic, Proc. Cryptographic Hardware and Embedded Systems (CHES), pp.62-75, 2004. ,
DOI : 10.1007/978-3-540-28632-5_5
URL : https://hal.archives-ouvertes.fr/lirmm-00108863
Study of modular inversion in RNS, Proc. Advanced Signal Processing Algorithms, Architectures, and Implementations XV, pp.247-255, 2005. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00106063
Double Level Montgomery Cox-Rower Architecture, New Bounds, Proc. 13th Smart Card Research and Advanced Application Conference (CARDIS), pp.139-153, 2014. ,
DOI : 10.1007/978-3-319-16763-3_9
URL : https://hal.archives-ouvertes.fr/hal-01098803
´ Etude théorique et implantation matérielle d'unités de calcul en représentation modulaire des nombres pour la cryptographie sur courbes elliptiques, 2014. ,
Opérateur matériel de tests de divisibilité par des petites constantes sur de très grands entiers, Proc. 15ème Symposium en Architectures nouvelles de machines (SympA), 2013. ,
Improving Modular Inversion in RNS Using the Plus-Minus Method, Proc. 15th Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.233-249, 2013. ,
DOI : 10.1007/978-3-642-40349-1_14
URL : https://hal.archives-ouvertes.fr/hal-00825745
Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC, Proc. 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.123-140, 2015. ,
DOI : 10.1007/978-3-662-48324-4_7
URL : https://hal.archives-ouvertes.fr/hal-01199155
Systolic VLSI Arrays for Polynomial GCD Computation, IEEE Transactions on Computers, vol.33, issue.8, pp.33731-736, 1984. ,
DOI : 10.1109/TC.1984.5009358
On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations, 2013 IEEE 21st Symposium on Computer Arithmetic, pp.219-228, 2013. ,
DOI : 10.1109/ARITH.2013.17
URL : https://hal.archives-ouvertes.fr/hal-00772613
FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction, Proc. 13th Cryptographic Hardware and Embedded Systems (CHES), pp.421-441, 2011. ,
DOI : 10.1007/978-3-642-23951-9_28
URL : https://hal.archives-ouvertes.fr/hal-00745016
Parallel FPGA implementation of RSA with residue number systems ? can side-channel threats be avoided? ?, Proc. 46th Midwest Symposium on Circuits and Systems (MWSCAS), pp.806-810, 2003. ,
Method and apparatus for public key exchange in a cryptographic system, 1992. ,