Generalized cache tiling for dataflow programs

Łukasz Domagała 1 Duco Van Amstel 1 Fabrice Rastello 1
1 CORSE - Compiler Optimization and Run-time Systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : The dataflow programming paradigm has facilitated the expression of a great number of algorithmic applications on embedded platforms in a wide variety of applicative domains. Whether it is a Domain Specific Language (DSL) or a more generalistic one, the dataflow paradigm allows to intuitively state the successive steps of an algorithm and link them through data communications. The optimization of cache-memory in this context has been a subject of interest since the early '90s as the reuse and communication of data between the agents of a dataflow program is a key factor in achieving a high-performance implementation within the reduced limits of embedded architectures. In order to improve data reuse among the dataflow agents we propose a modelisation of the communications and data usage within a dataflow program. Aside from providing an estimate of the amount of cache-misses that a given scheduling generates, this model allows us to specify the associated optimization problem in a manner that is identical to loop-nest tiling. Improving on the existing state-of-the-art methods we extend our tiling technique to include non-uniform dependencies on one of the dimensions of the iteration space. When applying the proposed technique to dataflow programs expressed within the StreamIt framework we are able to showcase significant reductions in the number of cache-misses for a majority of test-cases when compared to existing optimizations.
Type de document :
Communication dans un congrès
Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Jun 2016, Santa Barbara, United States. pp.10, 2016, Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems. 〈10.1145/2907950.2907960〉
Liste complète des métadonnées

https://hal.inria.fr/hal-01336172
Contributeur : Duco Amstel <>
Soumis le : mercredi 22 juin 2016 - 16:45:37
Dernière modification le : mercredi 14 décembre 2016 - 01:02:50

Identifiants

Collections

Citation

Łukasz Domagała, Duco Van Amstel, Fabrice Rastello. Generalized cache tiling for dataflow programs. Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Jun 2016, Santa Barbara, United States. pp.10, 2016, Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems. 〈10.1145/2907950.2907960〉. 〈hal-01336172〉

Partager

Métriques

Consultations de la notice

177