A. Alameldeen and D. Wood, Adaptive Cache Compression for High-Performance Processors, Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004.

A. Seznec, A case for two-way skewed-associative caches, Proc. of the 20th annual Intl. Symp. on Computer Architecture, 1993.
DOI : 10.1109/isca.1993.698558

A. Seznec, Concurrent support of multiple page sizes on a skewed associative TLB, IEEE Transactions on Computers, vol.53, issue.7, 2004.
DOI : 10.1109/TC.2004.21

A. Seznec and F. Bodin, Skewed-associative caches, Proceedings of PARLE' 93, 1993.
DOI : 10.1007/3-540-56891-3_24
URL : https://hal.archives-ouvertes.fr/inria-00074902

A. Alameldeen, Variability in Architectural Simulations of Multi-threaded Workloads, Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture, 2003.

A. Seznec, Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio, Proceedings of 21 International Symposium on Computer Architecture, 1994.
DOI : 10.1109/ISCA.1994.288133

A. Arelakis and P. Stenstrom, SC2, Proceedings of the 41st Annual International Symposium on Computer Architecture, 2014.
DOI : 10.1145/2678373.2665696

B. Abali, H. Franke, X. Shen, D. E. Poff, and T. Smith, Performance of hardware compressed main memory, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001.
DOI : 10.1109/HPCA.2001.903253

C. Bienia and K. Li, PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors, Workshop on Modeling, Benchmarking and Simulation, 2009.

D. Sanchez and C. Kozyrakis, The ZCache: Decoupling Ways and Associativity, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010.
DOI : 10.1109/MICRO.2010.20

R. Normalized, L. Basline, and . Fig, YACC performance using RRIP Yet Another Compressed Cache: A Low Cost Yet Effective Compressed Cache, ACM Transactions on xxxxxxxx Month YYYY, vol.12

E. Hallnor and S. Reinhardt, A Unified Compressed Memory Hierarchy, 11th International Symposium on High-Performance Computer Architecture, 2005.
DOI : 10.1109/HPCA.2005.4

G. Pekhimenko, V. Seshadri, Y. Kim, H. Xin, O. Mutlu et al., Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework, Annual IEEE/ACM International Symposium on Microarchitecture, 2013.

J. Lee, W. Hong, and S. Kim, An on-chip cache compression technique to reduce decompression overhead and design complexity, Journal of Systems Architecture, vol.46, issue.15, 2000.
DOI : 10.1016/S1383-7621(00)00030-8

J. Zebchuk, E. Safi, and A. Moshovos, A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), 2007.
DOI : 10.1109/MICRO.2007.14

J. Rothman and A. Smith, The pool of subsectors cache design, Proceedings of the 13th international conference on Supercomputing , ICS '99, 1999.
DOI : 10.1145/305138.305156

J. Dusser and A. Seznec, Decoupled zero-compressed memory, Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC '11, 2011.
DOI : 10.1145/1944862.1944876
URL : https://hal.archives-ouvertes.fr/inria-00468354

J. Dusser, T. Piquet, and A. Seznec, Zero-content augmented caches, Proceedings of the 23rd international conference on Conference on Supercomputing, ICS '09, 2009.
DOI : 10.1145/1542275.1542288
URL : https://hal.archives-ouvertes.fr/inria-00337742

J. Yang and R. Gupta, Frequent value locality and its applications, ACM Transactions on Embedded Computing Systems, vol.1, issue.1, 2002.
DOI : 10.1145/581888.581894

L. Villa, M. Zhang, and K. Asanovic, Dynamic zero compression for cache energy reduction, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, 2000.

M. Ekman and P. Stenstrom, A robust main-memory compression scheme, 32nd International Symposium on Computer Architecture (ISCA'05), 2005.
DOI : 10.1109/ISCA.2005.6

N. S. Kim, T. Austin, and T. Mudge, Low-Energy Data Cache Using Sign Compression and Cache Line Bisection, Second Annual workshop on Memory Performance Issues, 2002.

S. Sardashti and D. A. Wood, Decoupled compressed cache, Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, 2013.
DOI : 10.1145/2540708.2540715

S. Baek, H. Gyu-lee, C. Nicopoulos, J. Lee, and J. Kim, ECM: Effective Capacity Maximizer for High-Performance Compressed Caching, Proceedings of IEEE Symposium on High-Performance Computer Architecture, 2013.

S. Sardashti and D. A. Wood, Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization, IEEE Micro Top Picks from the 2013 Computer Architecture Conferences, 2013.
DOI : 10.1109/MM.2014.42

A. Sardashti, D. Seznec, and . Wood, Skewed Compressed Caches, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014.
DOI : 10.1109/MICRO.2014.41

S. Kim, J. Kim, J. Lee, and S. Hong, Residue cache, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, 2011.
DOI : 10.1145/2155620.2155670

V. Aslot, M. Domeika, R. Eigenmann, G. Gaertner, W. B. Jones et al., SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance, Workshop on OpenMP Applications and Tools, 2001.
DOI : 10.1007/3-540-44587-0_1

X. Chen, L. Yang, R. P. Dick, L. Shang, and H. Lekatsas, C-pack: a high-performance microprocessor cache compression algorithm, IEEE Transactions on VLSI Systems, 2010.

A. Jaleel, K. B. Theobald, C. Simon, J. Steely-jr, and . Emer, High Performance Cache Replacement Using Re-Reference Interval Prediction, 2010.

J. Ziv and A. Lempel, A universal algorithm for sequential data compression, IEEE Transactions on Information Theory, vol.23, issue.3, pp.337-343, 1977.
DOI : 10.1109/TIT.1977.1055714

J. Ziv and A. Lempel, Compression of individual sequences via variable-rate coding, IEEE Transactions on Information Theory, vol.24, issue.5, pp.530-536, 1978.
DOI : 10.1109/TIT.1978.1055934

A. David and . Huffman, A Method for the Construction of Minimum-Redundancy Codes, Proc. Inst. Radio Engineers, pp.1098-1101, 1952.

J. S. Vitter, Design and analysis of dynamic Huffman codes, Journal of the ACM, vol.34, issue.4, pp.825-845, 1987.
DOI : 10.1145/31846.42227

G. Pekhimenko, V. Seshadri, O. Mutlu, P. B. Gibbons, M. A. Kozuch et al., Base-delta-immediate compression, Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12, pp.377-388, 2012.
DOI : 10.1145/2370816.2370870