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Conference papers

TAGE-SC-L Branch Predictors Again

André Seznec 1
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Outline In this study, we explore the performance limits of these TAGE-SC-L predictors for respectively 8Kbytes and 64Kbytes of storage budget. For a 8KB storage budget, our submitted predictor used most of its storage budget on the TAGE predictor, features a very small loop predictor LP and a neural statistical cor-rector exploiting global history path and very limited local history. The submitted 8Kbytes predictor achieves 4.991 MPKI on the CBP-5 train traces. With a larger storage budget, one can invest more significant storage budget in the adjunct predictors. The submitted 512Kbits TAGE-SC-L predictor features a TAGE predictor, a loop predictor LP and a quite complex (57 Kbits) neural statistical corrector that exploits various form of local histories , global branch history, IMLI counter [12]. The submitted 64KB TAGE-SC-L predictor achieves 3.986 MPKI on the CBP-5 train traces.
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Submitted on : Thursday, August 18, 2016 - 10:32:13 AM
Last modification on : Thursday, January 20, 2022 - 5:31:56 PM


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  • HAL Id : hal-01354253, version 1


André Seznec. TAGE-SC-L Branch Predictors Again. 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. ⟨hal-01354253⟩



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